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SN65LVDM22PWG4 Datasheet(PDF) 3 Page - Texas Instruments |
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SN65LVDM22PWG4 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 14 page www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC S0, S1 Input 50 Ω 300 k Ω 7 V VCC 1DE, 2DE Input 50 Ω 300 k Ω 7 V VCC 300 k Ω 300 k Ω 7 V 7 V A Input B Input VCC 7 V Y or Z Output 5 Ω 10 k Ω ABSOLUTE MAXIMUM RATINGS SN65LVDS22 SN65LVDM22 SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. over operating free-air temperature range (unless otherwise noted)(1) UNIT Supply voltage range, VCC (see Note (2)) –0.5 V to 4 V (DE, S0, S1) –0.5 V to 6 V Voltage range (Y, Z, A, and B) –0.5 V to 4 V A, B, Y, Z and GND (see Note (3)) Class 3, A:12 kV, B:600 V Electrostatic discharge All pins Class 3, A:5 kV, B:500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with MIL-STD-883C Method 3015.7. 3 Submit Documentation Feedback |
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