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SN65MLVD047DR Datasheet(PDF) 4 Page - Texas Instruments |
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SN65MLVD047DR Datasheet(HTML) 4 Page - Texas Instruments |
4 / 17 page www.ti.com DEVICE ELECTRICAL CHARACTERISTICS SN65MLVD047 SLLS606A – MARCH 2004 – REVISED JULY 2005 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT LVTTL (EN, EN, 1A:4A) |IIH| High-level input current VIH = 2 V or VCC 0 10 µA |IIL| Low-level input current VIL = GND or 0.8 V 0 10 µA Ci Input capacitance VI = 0.4 sin(30E6πt) + 0.5 V(3) 5 pF M-LVDS (1Y/1Z:4Y/4Z) |VYZ| Differential output voltage magnitude 480 650 mV See Figure 2 Change in differential output voltage magnitude ∆|V YZ| –50 50 mV between logic states VOS(SS) Steady-state common-mode output voltage 0.8 1.2 V Change in steady-state common-mode output ∆V OS(SS) See Figure 3 –50 50 mV voltage between logic states VOS(PP) Peak-to-peak common-mode output voltage 150 mV Maximum steady-state open-circuit output volt- VY(OC) 0 2.4 V age See Figure 7 Maximum steady-state open-circuit output volt- VZ(OC) 0 2.4 V age VP(H) Voltage overshoot, low-to-high level output 1.2 VSS V See Figure 5 VP(L) Voltage overshoot, high-to-low level output –0.2 VSS V Differential short-circuit output current magni- |IOS| See Figure 4 24 mA tude –1.4 V ≤ (V Y or VZ) ≤ 3.8 V, IOZ High-impedance state output current –15 10 µA Other output = 1.2 V –1.4 V ≤ (V Y or VZ) ≤ 3.8 V, IO(OFF) Power-off output current –10 10 µA Other output = 1.2 V, VCC = 0 V VY or VZ = 0.4 sin(30E6πt) + 0.5 V,(3) CY or CZ Output capacitance 3 pF Other input at 1.2 V, driver disabled VYZ = 0.4 sin(30E6πt) V,(3) CYZ Differential output capacitance 2.5 pF Driver disabled CY/Z Output capacitance balance, (CY/CZ) 0.99 1.01 (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) All typical values are at 25 °C and with a 3.3-V supply voltage. (3) HP4194A impedance analyzer (or equivalent) 4 |
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