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DEVICE ELECTRICAL CHARACTERISTICS

SN65MLVD047

SLLS606A – MARCH 2004 – REVISED JULY 2005

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MAX

UNIT

LVTTL (EN, EN, 1A:4A)

High-level input current

0

10

µA

Low-level input current

0

10

µA

Input capacitance

5

pF

M-LVDS (1Y/1Z:4Y/4Z)

Differential output voltage magnitude

480

650

mV

See Figure 2

Change in differential output voltage magnitude

∆|V

–50

50

mV

between logic states

Steady-state common-mode output voltage

0.8

1.2

V

Change in steady-state common-mode output

∆V

OS(SS)

See Figure 3

–50

50

mV

voltage between logic states

Peak-to-peak common-mode output voltage

150

mV

Maximum steady-state open-circuit output volt-

0

2.4

V

age

See Figure 7

Maximum steady-state open-circuit output volt-

0

2.4

V

age

Voltage overshoot, low-to-high level output

V

See Figure 5

Voltage overshoot, high-to-low level output

V

Differential short-circuit output current magni-

See Figure 4

24

mA

tude

–1.4 V

≤ (V

High-impedance state output current

–15

10

µA

Other output = 1.2 V

–1.4 V

≤ (V

Power-off output current

–10

10

µA

Output capacitance

3

pF

Other input at 1.2 V, driver disabled

Differential output capacitance

2.5

pF

Driver disabled

0.99

1.01

(1)

The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

(2)

All typical values are at 25

°C and with a 3.3-V supply voltage.

(3)

HP4194A impedance analyzer (or equivalent)

4