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MT93L04AG2 Datasheet(PDF) 9 Page - Zarlink Semiconductor Inc |
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MT93L04AG2 Datasheet(HTML) 9 Page - Zarlink Semiconductor Inc |
9 / 56 page MT93L04 Data Sheet 9 Zarlink Semiconductor Inc. Test_En_d2 ICO V5 Internal Connection. Connected to VSS for normal operation RESETB_d2 Signal Y4 Device Reset (Schmitt Trigger Input). An active low resets the device and puts the MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. IRQB_d2 Signal U5 Interrupt Request (Open Drain Output). This output goes low when an interrupt occurs in any channel. IRQ returns high when all the interrupts have been read from the Interrupt FIFO Register. A pull-up resistor (1 K typical) is required at this output. DSB_d2 Signal W5 Data Strobe (Input). This active low input works in conjunction with CS to enable the read and write operations. CSB_d2 Signal Y5 Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/WB_d2 Signal V6 Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. DTAB_d2 Signal U6 Data Transfer Acknowledgment (Open Drain Output). This active low output indicates that a data bus transfer is completed. A pull-up resistor (1 K typical) is required at this output. D(0)_d2 Signal W6 Data Bus D0 - D7 (Bidirectional). These pins form the 8-bit bidirectional data bus of the microprocessor port. D(1)_d2 Signal Y6 D(2)_d2 Signal V7 D(3)_d2 Signal W7 D(4)_d2 Signal Y7 D(5)_d2 Signal Y8 D(6)_d2 Signal W8 D(7)_d2 Signal V8 Pin Description (continued) Signal Name Signal Type BGA Ball # Signal Description |
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