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NWK914B Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
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NWK914B Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
3 / 9 page 3 NWK914D NRZ to MLT3 Encoder The serial data from the shifter then passes through an encoder which converts the NRZI binary data into the three level MLT-3 format for transmission by the 'TXO' outputs. Transmit Line Drivers There are two on-chip Line Drivers both of which share the output pins TXOP and TXON. The N10/100 pin is used to control which driver is active and allowed to drive the line. When held high the MLT-3 data is output by the 100Mb/s driver. This driver consists of differential current source outputs with programmable sink capability, designed to drive a nominal output impedance of 50 Ω. Output current is set by the value of an external resistor (RREF) between pin 'TXREF' and 'TXGND'. This resistor defines an internal reference current derived from an on-chip bandgap reference. Final output current at the 'TXO' outputs is a multiple of this current and is defined as:- I TXO(mA) = 52/RREF(kΩ) Transition times of the 'TXO' outputs are matched and internally limited to approx. 2.5ns to reduce EMI emissions. FUNCTIONAL DESCRIPTION The functional blocks within the device are shown in Fig. 3. These are described below:- Transmit Section Times Five Clock Multiplier 25MHz to 125MHz This circuit consists of a phase lock loop (PLL) that is operating at 125MHz, centre frequency. The 125MHz is divided by 5 to produce a 25MHz clock which is phase compared with a 25MHz crystal clock reference frequency which is input on pin REFCLK. The 25MHz clock (pin TXC) is then sent to the PCS layer to clock in in the 5 bit nibble data. Pins LFTA and LFTB are provided to set the VCO characteristics. The recommended loop filter components are shown in Fig.6. A control current is derived from the clock multiplier and is used by the receive clock recovery circuit to centre the PLL when no input data is present. Five Bit Nibble to 125MHz Shifter Data is input to the transmit side in 5 bit wide parallel form on pins TDAT0 through TDAT4. This NRZ data is clocked in on the positive edge of the 25MHz clock pin TXC. The parallel data is first loaded into a 5 bit wide register prior to being loaded into a 5 bit PISO where it is converted into a serial data stream. The last stage of the shifter incorporates a converter to change the data from NRZ to NRZI. Fig.3 System block diagram LBEN TTLGND1 TXREF REFCLK LOW VOLTAGE EQSEL RXIP RXIN SHUT DOWN SUBGND TXOP TXON 3 LEVEL TXGND RXV CC1 RXGND RXVCC 2 TXPLLVCC 125 TDLV CC RXPLLVCC TIMES FIVE CLOCK MULTIPLIER SIGNAL DETECT ADAPTIVE EQUALIZER MLT-3 to NRZI COMPARATORS NRZI MLT-3 to DIVIDE by FIVE CLOCK RDAT0 RDAT1 RDAT2 RDAT3 RDAT4 RXC TDAT0 TDAT1 TDAT2 TDAT3 TDAT4 TXC LFTB TEST N10/100 10TXIN 10TXIP CURRENT MHz REFERENCE LFRA NRZ to NRZI SHIFTER & NRZI to NRZ SDT BGAPVCC BGAPGND RDLV CC LFTA TTLVCC TXV CC TTLGND2 LFRB CLOCK PLL,125MHZ RECOVERY TTL TESTIP TXPLLGND RXPLLGND B AND GAP VOLTAGE REFERENCE SHIFTER & 100 Mb/s 10 Mb/s TTL TXOE |
Similar Part No. - NWK914B |
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Similar Description - NWK914B |
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