PDSP16116/A/MC

6

NORMAL MODE OPERATION

When the MBFP mode select input is held low the ‘Normal’

mode of operation is selected.

This mode supports all

Complex Multiply operations that do not require Block Floating

Point arithmetic.

Multiplier Satge

Complex two's complement fractional data is loaded into

the X and Y input registers via the X and Y Ports on the rising

edge of CLK. The Real and Imaginary components of the

fractional data are each assumed to have the following format

BIT NUMBER

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

WEIGHTING

S

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

2

-7

2

-8

2

-9

2

-10

2

-11

2

-12

2

-13

2

-14

2

-15

Where S = sign bit which has an effective weighting -20

The value of the 16 bit two’s complement word is

Value = (-1xS)+(bit14x2-1)+(bit13x2-2)+(bit12x2-3). . .

The X & Y port registers are individually enabled by the

CEX & CEY signals respectvely. If the registers are required

to be permanently enabled, then these signals may be tied to

ground. On each clock cycle the contents of the input registers

are passed to the four multipliers to start a new Complex

Multiply operation. Each Complex Multiply operation requires

four partial products (Xr x Yr), (Xr x Yi), (Xi x Yr), (Xi x Yi), all

of which are calculated in parallel by the four 16 x 16

Multipliers. Only one clock cycle is required to complete the

multiply stage before the Mutliplier results are loaded into the

Multiplier output registers for passing on to the Adder/

Subtractors in the next cycle. Each multiplier produces a 31

bit result with the duplicate sign bit eliminated. The format of

the output data from the Multipliers is

BIT NUMBER

30

29

28

27

26

25

24

. . .

7

6

5

4

3

2

1

0

WEIGHTING

S

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

. . .

2

-23

2

-24

2

-25

2

-26

2

-27

2

-28

2

-29

2

-30

The effective weighting of the sign bit is -20

Result Correction

Due to the nature of the fraction twos complement

representation it is possible to represent -1 exactly but not 1.

With conventional multipliers this causes a problem when -1

is multiplied by -1 as the multiplier produces an incorrect

result. The PDSP16116 includes a trap to ensure that the

most positive number (value = 1.2-30), (hex = 7FFFFFFFF) is

subsituted for the incorrect result. The multiplier result is

therefore always a (correct) fractional value.

Complex Conjugation

Either the X or Y input data may be complex conjugated by

asserting the CONX or CONY signals respectively. Asserting

either of these signals has the effect of inverting (multiplying

by -1) the imaginary component of the respective input. Table

3 shows the effect of CONX and CONY on the X and Y inputs.

CONX

low

high

low

high

CONY

low

low

high

high

OPERATION

(XR+XI)x(YR+YI)

(XR+XI)x(YR-YI)

(XR-XI)x(YR+YI)

Invalid

FUNCTION

X x Y

X x Conj Y

Conj X x Y

Invalid

Table 3 Conjugate Functions

Adder / Subtractor Stage

The 31 bit Real and Imaginary results from the Multipliers

are passed to two 32 bit Adder/Subtractors.

The Adder

calculates the imaginary result ((Xr x Yi) + (Xi x Yr)) and the

Subtractor calculates the Real result ((Xr x Yr) = (Xi x Yi)).

Each Adder/Subtractor produces a 32 bit result with the

following format.

BIT NUMBER

31

30

29

28

27

26

. . .

8

7

6

5

4

3

2

1

0

WEIGHTING

S

2

0

2

-1

2

-2

2

-3

2

-4

. . .

2

-22

2

-23

2

-24

2

-25

2

-26

2

-27

2

-28

2

-29

2

-30

The effective weighting of the sign bit is -21

Rounding

The ROUND control when asserted rounds the most

significant 16 bits of the full 32 bit result from the Adder/

Subtractor. If the ROUND signal is active (High), then bit 16

is set to a one, rounding the most significant 16 bits of the

Adder/Subractor result. (The least siginificant 16 bits are

unaffected). Inserting a one ensures that the rounding error

is never greater than 1LSB, and that no DC bias is introduced

as a result of the rounding processes.

The format of the Rounded result is;

BIT NUMBER

31

30

29

28

27

. . .

18

17

16

15

14

13

. . .

2

1

0

WEIGHTING

S

2

0

2

-1

2

-2

2

-3

. . .

2

-12

2

-13

2

-14

2

-15

2

16

2

-17

. . .

2

-28

2

-29

2

-30

LBS's

ROUNDED VALUE

The effective weighting of the sign is -21

Shifter

Each of the two Adder/Subtractors are followed by Shifters

controlled via the WTB control input. These shifters can each

apply four different shifts, however the same shift is applied to

both real and imaginary components. The four shift options

are:

i)

WTB1:0 = 11 Shift complex product one place to the left

giving a shifter output format:

BIT NUMBER

31

30

29

28

27

26

25

. . .

7

6

5

4

3

2

1

0

WEIGHTING

S

2

-1

2

-2

2

-3

2

-4

2

-5

2

-6

. . .

2

-24

2

-25

2

-26

2

-27

2

-28

2

-29

2

-30

2

-31

The effective weighting of the sign bit is -20