PDSP16318/16318A

3

FUNCTIONAL DESCRIPTION

The PDSP16318 is a Dual 20-bit Adder/Subtractor

configured to support Complex Arithmetic. The device may be

used with each of the adders allocated to real or imaginary

data (e.g. Complex Conjugation), the entire device allocated

to Real or Imaginary Data (e.g. Radix 2 Butterflys) or each of

the adders configured as accumulators and allocated to real

or imaginary data (Complex Filters). Each of these modes

ensures that a full 20MHz throughput is maintained through

both adders, the first and last mode illustrating true Complex

operation, where both real and imaginary data is handled by

the single device.

Both

Adder/Subtractors

may

be

controlled

independently via the ASR and ASI inputs. These controls

permit A + B, A - B, B - A or pass A operations, where the A

input to the Adder is derived from the input multiplexer. The

CLR control line allows the clearing of both accumulator

registers. The two multiplexers may be controlled via the MS

inputs, to select either new input data, or fed-back data from

the accumulator registers. The PDSP16318 contains an 8-

cycle deskew register selected via the DEL control. This

deskew register is used in FFT applications to ensure correct

phasing of data that has not passed through the PDSP16112

Complex Multiplier.

The 16-bit outputs from the PDSP16318 are derived from

the 20-bit result generated by the Adders. The three bit S2:0

input selects eight different shifted output formats ranging

from the most significant 16 bits of the 20-bit data, to the least

significant 13 bits of the 20-bit data. In this mode the 14th, 15th

and 16th bits of the output are set to zero. The shift selected

is applied to both adder outputs, and determines the function

of the OVR flag. The OVR flag becomes active when either of

the two adders produces a result that has more significant

digits than the MSB of the 16-bit output from the device. In this

manner all cases when invalid data appears on the output are

flagged.

Symbol

A15:0

B15:0

C15:0

D15:0

CLK

CEA

CEB

OEC

OED

OVR

ASR1:0

ASI1:0

CLR

MS

S2:0

DEL

VCC

GND

Description

Data presented to this input is loaded into the input register on the rising edge of CLK. A15 is the MSB.

Data presented to this input is loaded into the input register on the rising edge of CLK. B15 is the MSB

and has the same weighting as A15.

New data appears on this output after the rising edge of CLK. C15 is the MSB.

New data appears on this output after the rising edge of CLK. C15 is the MSB.

Common Clock to all internal registers

Clock enable: when low the clock to the A input register is enabled.

Clock enable: when low the clock to the B input register is enabled.

Output enable: Asynchronous 3-state output control: The C outputs are in a high impedance

state when this input is high.

Output enable: Asynchronous 3-state output control: The D outputs are in a high impedance

state when this input is high.

Overflow flag: This flag will go high in any cycle during which either the output data overflows the number

range selected or either of the adder results overflow. A new OVR appears after the rising edge of the

CLK.

Add/subtract Real: Control input for the 'Real' adder. This input is latched by the rising edge of clock.

Add/subtract Imag: Control input for the 'Imag' adder. This input is latched by the rising edge of clock.

Accumulator Clear: Common accumulator clear for both Adder/Subtractor units. This input is latched by

the rising edge of CLK.

Mux select: Control input for both adder multiplexers. This input is latched by the rising edge of CLK.

When high the feedback path is selected.

Scaling control: This input selects the 16-bit field from the 20-bit adder result that is routed to the outputs.

This input is latched by the rising edge of CLK.

Delay Control: This input selects the delayed input to the real adder for operations involving the

PDSP16112. This input is latched by the rising edge of CLK.

+5V supply: Both Vcc pins must be connected.

0V supply: Both GND pins must be connected.

Type

Input

Input

Output

Output

Input

Input

Input

Input

Input

Output

Input

Input

Input

Input

Input

Input

Power

Ground