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PDSP16488AMAACBR Datasheet(PDF) 9 Page - Zarlink Semiconductor Inc |
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PDSP16488AMAACBR Datasheet(HTML) 9 Page - Zarlink Semiconductor Inc |
9 / 30 page PDSP16488A MA 9 Fig.7 Pixel Input Delays Table 3 Internal Register Addressing Ta ble 4 Pipe line dalays Function Mode Reg A Mode Reg B Mode Reg C Mode Reg D Comparator LSB Comparator MSB Scale Value Pixels / Line LSB Pixels / Line MSB Hex. Addr 00 01 02 03 04 05 06 07 08 C0 - C15 C16 - C31 C32 - C47 C48 - C63 Unused 40 - 4F 50 - 5F 60 - 6F 70 - 7F 09 - 3F 2 3 45678 12 7 6 last 2 pixels intern- ally stored LINE STORE WRITES INHIBITED ACTIVE LINE PERIOD ASYNCHRONOUS BACK EDGE HRES CLOCK Set Up Time [SYNC] First pixel valid [B3 set] First pixel from line store valid configurations when the gain control is used. These delays are the the internal processing delays and do not include the delays needed to move a given size window completely into a field of interest. When multiple devices are needed, addi- tional delays are produced which must be calculated for the particular application. These delays are discussed in the applications section. The PDSP16488A contains facilities for outputing a delayed version of HRES to match any processing delay. Control register bits allow this delay to be selected from any value between 29 and 92 pixel clocks. The internal convolver sums, in each of the devices in the next row, must be delayed by this amount before they are added to results from the previous row. This is more conven- iently achieved by delaying data going into the line stores. The required cumulative delay with respect to the first horizontal stripe is then automatically obtained when more than two rows of devices are needed. Two bits in Control Register D are used to define one of four delay options. These delays have been selected to support systems needing from two to eight devices and are described in the applications section. COEFFICIENTS Sixty-four coefficients are stored internally and must be initially loaded from an external source. Table 3 gives the coefficient addresses within a device, with coefficent C0 specified by the least significant address and C63 by the most significant address. Table 5 shows the physical window posi- tion within the device which is allocated to each coefficient in the various modes of operation. Horizontally the coefficient positions correspond to the convolution process as if it were conceptually observed on a viewing screen, ie the left hand pixel is multiplied with C0. In the vertical direction the lines of coefficients are inverted with respect to a visual screen, ie the line starting with C0 is actually at the bottom of the visualized window. The coefficients may be provided from a Host CPU using conventional addressing, a read/write line, data strobe, and a chip enable. Alternatively, in stand alone systems, an EPROM may be used. A single EPROM can support up to 16 devices with no additional hardware. When windows are to be fabricated which are smaller than the maximum size that the device will provide in the required configuration, then the areas which are not to be used must contain zero coefficients. The pipeline delay will then be that of a completely filled window. TOTAL PIPELINE DELAY The total pipeline delay is dependent on the device configuration and the number of devices in the system. Table 4 gives the delays obtained with the various single device Data size Window Size Pipeline Delay 8 8 8 16 16 34 30 26 28 26 4x4 8x4 8x8 4x4 8x4 |
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