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PDSP16510AMA Datasheet(PDF) 6 Page - Zarlink Semiconductor Inc |
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PDSP16510AMA Datasheet(HTML) 6 Page - Zarlink Semiconductor Inc |
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6 / 24 page  PDSP16510A MA 6 block floating point shifting scheme, which is discussed later. Overflow can NEVER occur if the 3 bit option is chosen, but at the expense of worse dynamic range. When overflow does occur a flag is raised which can be read by the user ( see later discussion on scale tag bits ), and the results ignored. In addition all frequency bins are forced to zero to prevent any erroneous system response. Even with only 2 bit word growth poor dynamic range will be obtained if the data is simply reduced to 16 bits, and becomes worse when the incoming data does not fully occupy all the bits in the word. These problems are overcome in the PDSP16510, however, by a block floating point scheme which compensates for any unnecessary word growth. During each pass the number of sign bits in the largest result is recorded. Before the next pass, data is shifted left [multiplied by 2], once for every extra sign bit in this recorded sample. At least one component in the block then fully occu- pies the 16 bit word, and maximum data accuracy is preserved Up to four shifts are possible before every pass after the first, with a total of fifteen for the complete transform. At the end of the transform the number of left shifts that have occurred is indicated on S3:0. Lack of pins prevents a separate output being available to indicate that overflow has occurred in the 2 bit word growth option. For this reason the maximum number of compensating left shifts in this mode is restricted to 14. State 15 is then used to indicate that overflow has occurred. The first step in the butterfly calculation multiplies 16 bit data values with 16 bit sine/cosine values, to give 18 bit results. This increased word length preserves accuracy through the following adder network, and has been shown through simulations to be an optimum size for transform sizes up to 1024 points. This is particularly true when the input data is restricted to below 16 bits, as is necessary with practical A/ D converters with very high sampling rates. The bottom bit of this 18 bit word is forced to logical one and as such is a compromise between truncation and true rounding. It gives a lower noise floor in the outputs compared to simple truncation. To prevent any possibility of overflow during the butterfly calculation the word length is allowed to grow by one bit through each of the three adders. The least significant bit is always discarded in the first two adders . Sixteen bits are then chosen from the final adder in the manner discussed earlier, and the number of sign bits in the largest result is recorded for use in the following pass. Fig. 3 shows one of the four internal data paths which can compute a radix-4 butterfly in twelve system clock cycles. This equates to completing the butterfly in 3 cycles for the complete device. DATA TRANSFERS The data transfer mechanism to and from the internal WORKSPACE FFT DATA PATH LOAD TRANS- FORM INPUT DATA OUTPUT Fig. 5. RAM Organization with 1024 Point Transforms RAM has been designed for use in a wide variety of applica- tions. The provision of an asynchronous input strobe (DIS), allows data to be loaded without the need for additional external buffering. An asynchronous output strobe (DOS) also allows transformed data to be dumped with the sampling clock, this being particularly useful when the device is per- forming the inverse transform back to the time domain. Inputs and outputs are both supported by flag and enabling signals which allow transfers to be properly co-ordinated with the internal transform operation. In many applications the DIS and DOS inputs can be tied together and fed by the sampling clock. If the output rate must be higher than the input rate, as with multiple devices support- ing overlapped data samples, both strobes can still be con- nected together. The clock supplied should then be twice or four times the sampling clock, and an internal divider can be used to provide the correctly reduced input rate. The provision of a separate DOS pin does, however, allow the output rate to be asynchronous to the input rate, and therefore faster than strictly needed. Further output processing at higher rates is then possible if this is advantageous to system requirements. The internal workspace is double buffered when 256 point transforms are to be performed. A separate output buffer is also provided. These resources, together with separate input and output buses, allow new data to be loaded and old results to be dumped, whilst the present transform is being computed. Additional, external, input buffering is not needed to prevent loss of incoming data whilst a transform is being performed. When block overlapping is required, internally stored data will be re-used, and a proportionally smaller number of new samples need be loaded. Note that the internal window operator still functions correctly since it is actually applied during the first pass, and not whilst data is being loaded. The internal RAM organisation is shown in Fig. 4. It should be noted that the amount of overlap between I/O transfers and transforms is completely under the control of the system, since an input enable signal (INEN) and an output enable (DEN) can be used to initiate transfers. In the 1024 point mode there is insufficient workspace for Fig. 6. 1024 Point Transforms with I/P Buffer Fig. 4. RAM Organization with 256 Data Points WORKSPACE A WORKSPACE B FFT DATA PATH O/P BUFFER LOAD TRANS- FORM INPUT DATA LOAD IN LAST PASS D I R PDSP16510 AUX PDSP16540 BUCKET BUFFER GND WS RS REAL IMAG' DAV SYSTEM CLOCK WEN MD5:0 GND 510 PARAMETERS SAMPLE CLOCK POWER ON RESET RES GND |
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