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UR5515-TN5-R Datasheet(PDF) 5 Page - Unisonic Technologies |
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UR5515-TN5-R Datasheet(HTML) 5 Page - Unisonic Technologies |
5 / 8 page UR5515 CMOS IC UNISONICTECHNOLOGIESCO.,LTD 5 of 8 www.unisonic.com.tw QW-R502-056,A TYPICAL APPLICATION CIRCUIT R1= R2= 100KΩ COUT(min)=10µF(Ceramic) + 1000µF under the worst case testing condition CSS=1µF, CIN = 40µF(low ESR), CCNTL= 47µF APPLICATIONS INFORMATION Please note the point of thermal shutdown will be degraded by around 20℃while VCNTL equal to 5V compared with 3.3V. It is highly recommended that to use the 3.3V rail acted as the VCNTL in SOP-8 package. Nevertheless, this small footprint of PCB for plastic SOP-8 package is not enough to dissipate effectively the heat generated when operating at high current levels. In order to control die operating temperatures, the PCB layout should allow for maximum possible copper area at the four VCNTL pins. Besides, an appropriate power plane heat sink must be used to prevent overstepping maximum junction temperature. The recommended SMT is as below. The PCB heat sink copper area should be solder painted without masked. This approaches a "best case " pad heat sink . UTC UR5515 (SOP-8) Use vias to conduct the heat into the buried or backside of PCB layer. |
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