MC74HC175AN datasheet(4/10 Pages) ONSEMI

Part #	MC74HC175AN

Description	Quad D Flip?묯lop with Common Clock and Reset High?뭁erformance Silicon?묰ate CMOS

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MC74HC175A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

VCC

V

Test Conditions

Parameter

Symbol

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

VOL

Maximum Low−Level Output

Voltage

Vin = VIH or VIL

|Iout| v 20 mA

2.0

4.5

6.0

0.1

V

Vin = VIH or VIL

|Iout| v 2.4 mA

|Iout| v 4.0 mA

|Iout| v 5.2 mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

mA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 mA

6.0

4

40

160

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

– 55 to

25

_C

v 85_C

v 125_C

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

3.0

4.5

6.0

6

10

30

35

4.8

8.0

24

28

4

6

20

24

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock to Q or Q

(Figures 1 and 4)

2.0

3.0

4.5

6.0

150

75

26

22

190

90

32

28

225

110

38

33

ns

tPHL

Maximum Propagation Delay, Reset to Q or Q

(Figures 2 and 4)

2.0

3.0

4.5

6.0

125

70

22

19

155

85

27

24

190

110

34

30

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

16

110

36

22

19

ns

Cin

Maximum Input Capacitance

—

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Flip−Flop)*

Typical @ 25

°C, VCC = 5.0 V

pF

35

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High−Speed CMOS Data Book (DL129/D).

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