MC74HC541ANG datasheet(4/10 Pages) ONSEMI

Part #	MC74HC541ANG

Description	Octal 3?뭆tate Noninverting Buffer/Line Driver/Line Receiver High?뭁erformance Silicon?묰ate CMOS

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MC74HC541A

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4

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Condition

VCC

V

*55 to

25

_C

v85_C v125_C

Unit

VIH

Minimum High−Level Input Voltage

VOUT = 0.1 V

|IOUT| ≤ 20 mA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

V

VIL

Maximum Low−Level Input Voltage

VOUT = VCC − 0.1 V

|IOUT| ≤ 20 mA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

V

VOH

Minimum High−Level Output Voltage

VIN = VIL

|IOUT| ≤ 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

VIN = VIL

|IOUT| ≤ 3.6 mA

|IOUT| ≤ 6.0 mA

|IOUT| ≤ 7.8 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL

Maximum Low−Level Output Voltage

VIN = VIH

|IOUT| ≤ 20 mA

2.0

4.5

6.0

0.1

V

VIN = VIH

|IOUT| ≤ 3.6 mA

|IOUT| ≤ 6.0 mA

|IOUT| ≤ 7.8 mA

3.0

4.5

6.0

0.26

0.33

0.40

IIN

Maximum Input Leakage Current

VIN = VCC or GND

6.0

$0.1

$1.0

mA

IOZ

Maximum 3−State Leakage Current

Output in High Impedance State

VIN = VIL or VIH

VOUT = VCC or GND

6.0

$0.5

$5.0

$10.0

mA

ICC

Maximum Quiescent Supply

Current (per Package)

VIN = VCC or GND

IOUT = 0 mA

6.0

4

40

160

mA

8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

VCC

V

*55 to

25

_C

v85_C

v125_C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 3 and 5)

2.0

3.0

4.5

6.0

80

30

18

15

100

40

23

20

120

55

28

25

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Output Y

(Figures 4 and 6)

2.0

3.0

4.5

6.0

110

45

25

21

140

60

31

26

165

75

38

31

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Output Y

(Figures 4 and 6)

2.0

3.0

4.5

6.0

110

45

25

21

140

60

31

26

165

75

38

31

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 3 and 5)

2.0

3.0

4.5

6.0

60

22

12

10

75

28

15

13

90

34

18

15

ns

CIN

Maximum Input Capacitance

10

pF

COUT

Maximum 3−State Output Capacitance (High Impedance State Output)

15

pF

9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed

CMOS Data Book (DL129/D).

Typical @ 25

°C, VCC = 5.0 V, VEE = 0 V

CPD

Power Dissipation Capacitance (Per Buffer) (Note 10)

35

pF

10. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON

Semiconductor High−Speed CMOS Data Book (DL129/D).

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