Inputs

Outputs

CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X

X

H

X

X

X

HH

HH

HH

HH

X

H

X

X

X

X

HH

HH

HH

HH

L

X

X

X

X

X

HH

HH

HH

HH

H

L

L

L

L

L

L

H

HH

HH

HH

H

L

L

L

L

H

H

L

HH

HH

HH

H

L

L

L

H

L

HH

L

H

HH

HH

H

L

L

L

H

H

HH

H

L

HH

HH

H

L

L

H

L

L

HH

HH

L

H

HH

H

L

L

H

L

H

HH

HH

H

L

HH

H

L

L

H

H

L

HH

HH

HH

L

H

H

L

L

H

H

H

HH

HH

HH

H

L

FUNCTION TABLE

H = high level (steady state)

L = low level (steady state)

X = don’t care

MC74HCT138A

http://onsemi.com

2

LOGIC DIAGRAM

7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Y7

9

10

11

12

13

14

15

3

2

1

CS1

CS2

A0

A1

A2

ACTIVE−LOW

OUTPUTS

ADDRESS

INPUTS

CS3

CHIP−

SELECT

INPUTS

5

4

6

PIN 8 = GND

PIN ASSIGNMENT

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

A0

CS2

A2

A1

Y7

CS1

CS3

GND

Y3

Y2

Y1

Y0

Y5

Y4

Y6

Design Criteria

Value

Units

Internal Gate Count*

30.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

mW

Speed Power Product

.0075

pJ

*Equivalent to a two−input NAND gate.

ORDERING INFORMATION

Device

Package

MC74HCT138AN

PDIP−16

500 Units / Box

MC74HCT138ANG

PDIP−16

(Pb−Free)

500 Units / Box

MC74HCT138AD

SOIC−16

48 Units / Rail

MC74HCT138ADG

SOIC−16

(Pb−Free)

48 Units / Rail

MC74HCT138ADR2

SOIC−16

2500 Units / Tape & Reel

MC74HCT138ADR2G

SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

MC74HCT138ADTR2

TSSOP−16*

2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.