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MC74HC4020ADR2G Datasheet(PDF) 5 Page - ON Semiconductor |
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MC74HC4020ADR2G Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 10 page MC74HC4020A http://onsemi.com 5 TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit Unit −55 to 25 °C ≤85°C ≤125°C trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 30 20 5 4 40 25 8 6 50 30 12 9 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 70 40 15 13 80 45 19 16 90 50 24 20 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). PIN DESCRIPTIONS INPUTS Clock (Pin 10) Negative−edge triggering clock input. A high−to−low transition on this input advances the state of the counter. Reset (Pin 11) Active−high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all Q outputs low. OUTPUTS Q1, Q4—Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3) Active−high outputs. Each Qn output divides the Clock input frequency by 2N. SWITCHING WAVEFORMS tf Clock Q1 VCC GND 90% 50% 10% tr tw 90% 50% 10% tPHL 1/fMAX tPLH tTLH tTHL Clock VCC GND tw trec 50% Figure 3. Reset VCC GND 50% Any Q 50% tPHL Figure 4. |
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