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X2TLK2218GPV Datasheet(PDF) 9 Page - Texas Instruments |
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X2TLK2218GPV Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 39 page  www.ti.com Management Data Interface Signals JTAG Interface Signals TLK2218 SLLS734 – FEBRUARY 2007 SIGNAL LOCATION TYPE DESCRIPTION RDHG[7:0] T12, U12, T11, LVCMOS Receive data channels G and H. The parallel data is clocked out of the transceiver on the U11, T10, output rising and falling edges of the receive clock. U10, T9, U9 In multiplexed channel mode, data for channel H is aligned to the rising edge of RCLK and data for channel G is aligned to the falling edge of RCLK (see Figure 6 for clarity). In nibble mode, data is output least-significant nibble first, aligned to the falling edge of the receive clock, followed by the most significant nibble aligned to the rising edge. Channel G is output on RDHG[4] and channel H is output on RDHG[9:5]. When CODE = high, RDHG3 acts as the K-flag bit for channel G on the rising edge of RCLK. These terminals are internally series terminated to provide direct connection to a 50- Ω transmission line. RDHG8 U13 LVCMOS Receive data/K-flag, channels G and H. The parallel data is clocked out of the transceiver output on the rising and falling edges of receive clock. In multiplexed channel mode, when CODE = low, this terminal is the 9th bit of a 10-bit word received. When CODE = high, this terminal acts as the K-flag bit. When RDFE8 = high, this terminal indicates that the data on RDHG[7:0] is a K-character. In nibble interface mode, when CODE = low, this terminal is the 4th and 9th bits of a 10-bit word received on channel H. When CODE = high, this terminal acts as the 4th bit on the falling edge and as the K-flag bit on the rising edge for channel H. When RDHG8 = high, this terminal indicates that the data RDHG[7:0], output on the rising and falling edges of the receive clock, is a K-character. This terminal is internally series-terminated to provide direct connection to a 50- Ω transmission line. RDHG9 T13 LVCMOS Receive data 9, channels G and H. The parallel data is clocked out of the transceiver on output the rising and falling edges of the receive clock. In multiplexed channel mode, when CODE = low, this terminal is the 10th bit of a 10-bit word received. In nibble interface mode, when CODE = low, this terminal is the 5th and 10th bits of a 10-bit word received on channel H. This terminal is internally series-terminated to provide direct connection to a 50- Ω transmission line. SIGNAL LOCATION TYPE DESCRIPTION MDIO J1 LVCMOS Management data I/O. MDIO is the bidirectional serial data path for the transfer of I/O with management data to and from the protocol device. P/U MDC H3 LVCMOS Management data clock. MDC is the clock reference for the transfer of management data input to and from the protocol device. DVAD[4:0] D12, D11, LVCMOS Management address. Device address: DVAD[4:0] is the externally set physical address P13, R13, R12 input with given to this device, used to distinguish one device from another. This address is latched P/D on the rising edge of RESET. SIGNAL LOCATION TYPE DESCRIPTION TCK C10 LVCMOS Test clock. IEEE 1149.1 (JTAG) TCK is used to clock state information and test data into input and out of the device during the operation of the test port. TDI C9 LVCMOS Test data input. IEEE 1149.1 (JTAG) TDI is used to shift test data and test instructions into input with the device serially during the operation of the test port. P/U TDO C7 LVCMOS Test data output. IEEE 1149.1 (JTAG) TDO is used to shift test data and test instructions output out of the device serially during operation of the test port. When the JTAG port is not in use, TDO is in a high-impedance state. TMS C11 LVCMOS Test mode select. IEEE 1149.1 (JTAG) TMS is used to control the state of the internal input with test-port controller. P/U TRST D8 LVCMOS JTAG reset. IEEE 1149.1 (JTAG) TRST is used to reset the internal JTAG controller. input with P/U 9 Submit Documentation Feedback |
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