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74F280SJ Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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74F280SJ Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Unit Loading/Fan Out Truth Table H = HIGH Voltage Level L = LOW Voltage Level Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL I0–I8 Data Inputs 1.0/1.0 20 µA/−0.6 mA ∑ O Odd Parity Output 50/33.3 −1 mA/20 mA ∑ E Even Parity Output 50/33.3 −1 mA/20 mA Number of Outputs HIGH Inputs ∑ Even ∑ Odd I0–I8 0, 2, 4, 6, 8 H L 1, 3, 5, 7, 9 L H |
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