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MC74VHC1GT14 Datasheet(PDF) 1 Page - ON Semiconductor

Part # MC74VHC1GT14
Description  Schmitt?뭈rigger Inverter / CMOS Logic Level Shifter LSTTL?묬ompatible Inputs
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74VHC1GT14 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2007
February, 2007 − Rev. 12
1
Publication Order Number:
MC74VHC1GT14/D
MC74VHC1GT14
Schmitt−Trigger Inverter /
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The MC74VHC1GT14 is a single gate CMOS Schmitt−trigger
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT14 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT14 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction
caused by supply voltage − input/output voltage mismatch, battery
backup, hot insertion, etc. The MC74VHC1GT14 can be used to
enhance noise immunity or to square up slowly changing waveforms.
Features
High Speed: tPD = 4.5 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 100; Equivalent Gates = 25
Pb−Free Packages are Available
VCC
NC
IN A
OUT Y
GND
IN A
OUT Y
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
1
2
3
4
5
1
PIN ASSIGNMENT
1
2
3
GND
NC
IN A
4
5VCC
OUT Y
FUNCTION TABLE
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
H
A Input
Y Output
H
L
http://onsemi.com
SC−88A/SC70−5/SOT−353
DF SUFFIX
CASE 419A
TSOP−5/SOT23−5/SC59−5
DT SUFFIX
CASE 483
1
5
1
5
VC M
G
G
VC
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
1
5
VC M
G
G


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