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MC74VHC373 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC74VHC373 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2005 January, 2005 − Rev. 6 1 Publication Order Number: MC74VHC373/D MC74VHC373 Octal D−Type Latch with 3−State Output The MC74VHC373 is an advanced high speed CMOS octal latch with 3−state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. This 8−bit D−type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems. Features • High Speed: t PD = 5.0 ns (Typ) at VCC = 5.0 V • Low Power Dissipation: I CC = 4.0 mA (Max) at TA = 25°C • High Noise Immunity: V NIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2.0 V to 5.5 V Operating Range • Low Noise: V OLP = 0.9 V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300 mA • ESD Performance: HBM > 2000 V; Machine Model > 200 V • Chip Complexity: 186 FETs or 46.5 Equivalent Gates • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAMS SOIC−20 WIDE DW SUFFIX CASE 751D SOEIAJ−20 M SUFFIX CASE 967 1 20 74VHC373 AWLYYWW TSSOP−20 DT SUFFIX CASE 948E 1 20 1 20 1 20 VHC 373 ALYW 1 20 PIN ASSIGNMENT Q2 D1 D0 Q0 OE GND Q3 D3 D2 Q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 Q6 D6 D7 Q7 VCC LE Q4 D4 D5 Q5 http://onsemi.com 20 1 VHC373 AWLYYWW See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week |
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