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SP6133 Datasheet(PDF) 4 Page - Sipex Corporation |
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SP6133 Datasheet(HTML) 4 Page - Sipex Corporation |
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4 / 20 page  4 Oct 24-06 Rev L SP633 Synchronous Buck Controller © 2006 Sipex Corporation ELECTRICAL SPECIFICATIONS Unlessotherwisespecified:-40°C<TAMB<+85°C,4.5V<VCC <5.5V,BST=VCC,SWN = PGND = GND = 0.0V, UVIN = 3.0V, CVCC = 0.µF, CCOMP = 0.µF, CGH = CGL = 3.3nF, CSS = 50nF. PARAMETER MIN TYP MAX UNITS CONDITIONS OUTPUT: NFET GATE DRIVERS GH & GL Rise Times 35 50 ns Measured 0% to 90% GH & GL Fall Times 30 40 ns Measured 90% to 0% GL to GH Non Overlap Time 45 70 ns GH & GL Measured at 2.0V SWN to GL Non Overlap Time 25 40 ns Measured SWN = 00mV to GL = 2.0V GH & GL Pull Down Resistance 5 50 85 KΩ Driver Pull Down Resistance .5 .9 Ω Driver Pull Up Resistance 2.5 3.9 Ω BLOCk DIAGRAM NON SYNC. STARTUP 220ms Delay 300 kHZ FAULT 0.1V 0.25V SOFTSTARTINPUT 135ºC OFF 145ºC ON 50KΩ 140KΩ 1.0V OFF 1.7V ON 4.05 V OFF 4.25 V ON FAULT R FAULT 6 EN 1 uA VCC VCC 3 GND ENABLE COMPARATOR COMPARATOR 1.6 V SS GL HOLD OFF CLK CLOCK PULSE GENERATOR Q S RESET DOMINANT QPWM SYNCHRONOUS DRIVER 13 12 11 1 2 PGND BST 7 9 10 15 14 16 8 5 2.8 V 1.3 V RAMP =1V VFB Power Good PWRGD 0.72 V OFF 0.74 V ON VPOS THERMAL AND OVER CURRENT PROTECTION UVLO COMPARATORS VCC UVLO HICCUP FAULT REFOK COUNTER CLR CLK ISP ISN 60 mV OVER CURRENT DETECTION DETECTION VFBINT SHORTCIRCUIT Q DOMINANT R S SET SHUTDOWN THERMAL VIN REFOK CORE 0.8V UVIN VIN UVLO 2.50 V ON 2.20 V OFF REGULATOR LINEAR 5V REFERENCE POWER FAULT VCC POS REF FAULT VCC SS 10 uA VCC VFBINT 4 VFB GL PWM LOOP COMP VPOS Gm Gm ERROR AMPLIFIER GH SWN |
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