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MC100EL14DW Datasheet(PDF) 2 Page - ON Semiconductor |
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MC100EL14DW Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC100EL14 http://onsemi.com 2 Figure 1. Logic Diagram and Pinout Assignment Q1 Q2 Q3 Q4 17 18 16 15 14 13 12 4 3 5678 9 VCC 11 10 Q4 Q3 Q2 Q1 NC SCLK CLK CLK VBB SEL VEE D Q 1 0 Q0 19 20 2 1 VCC Q0 EN * All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Table 1. PIN DESCRIPTION PIN FUNCTION CLK, CLK ECL Diff Clock Inputs SCLK ECL Scan Clock Input EN ECL Sync Enable SEL ECL Clock Select Input Q0−4, Q0−4 ECL Diff Clock Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect Table 2. FUNCTION TABLE CLK* SCLK* SEL* EN* Q L H X X X X X L H X L L H H X L L L L H L H L H L (Note ) 1. On next negative transition of CLK or SCLK **Pins will default low when left open. Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charge Device Model > 2 kV > 200 V > 4 kV Moisture Sensitivity (Note 2) Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 303 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. |
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