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MC100EL90 Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100EL90 Datasheet(HTML) 1 Page - ON Semiconductor |
1 / 5 page © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 3 1 Publication Order Number: MC100EL90/D MC100EL90 −3.3V / −5VTriple ECL Input to PECL Output Translator Description The MC100EL90 is a triple ECL to PECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to standard +5 V differential PECL output signals. To accomplish the level translation, the EL90 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins, as expected, are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 mF capacitors. Under open input conditions, the D input will be biased at VEE/2 and the D input will be pulled to VEE. This condition will force the Q output to a LOW, ensuring stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series Contains Temperature Compensation Features • 500 ps Propagation Delays • Operating Range: VCC= 4.75 V to 5.25 V; VEE= −3.0 V to −5.5 V; GND= 0 V • Q Output will Default LOW with Inputs Open or at VEE • Internal Input Pulldown Resistors • ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 1.125 in, Oxygen Index: 28 to 34 • Transistor Count = 261 devices • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAM* http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ORDERING INFORMATION SO−20 WB SUFFIX CASE 751D A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G= Pb−Free Package 20 1 100EL90 AWLYYWWG |
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