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SP8852E Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc |
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SP8852E Datasheet(HTML) 7 Page - Zarlink Semiconductor Inc |
7 / 15 page 7 SP8852E the charge pump outputs when high. During this period the VCO control voltage will be maintained by the loop filter components around the loop amplifier, but due to the com- bined effects of the amplifier input current and charge pump leakage a gradual change will occur. In order to reduce the change, the duration of the strobe pulse should be minimised. Selection of a loop amplifier with low input current will reduce the VCO voltage droop during the strobe pulse and result in minimum reference sidebands from the synthesiser. Reference Input The reference source can be either driven from an external sine or square wave source of up to 100MHz or a crystal can be connected as shown in Fig. 5. Phase Comparator and Charge Pump The SP8852E has a digital phase/frequency comparator driving a charge pump with programmable current output. The charge pump current level at the minimum gain setting is approximately equal to the current fed into the RSET input, pin 19, and can be increased by programming the bus according to Table 2 by up to 4 times. VCC21·6V RSET Pin 19 current = Phase detector gain = IPIN19 (mA)3multiplication factor 2p mA/rad Sense bit (bit 12) 1 0 Pin 20 Current source Current sink Output for RF phase lag Table 3 Bit 11 0 0 1 1 Bit 10 0 1 0 1 Phase detector state Enabled, FPD and FREF off Enabled, FPD and FREF on Disabled by lock detect, FPD and FREF on Disabled, FPD and FREF on The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pump output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pullup resistor is used in place of the LED. A small capacitor connected form the C-LOCK DETECTOR pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. To allow for control direction changes introduced by the design of the PLL, bit 12 on the input bus address 0 can be programmed to reverse the sense of the phase detector by transposing the FPD and FREF connections. In order that any external phase detector will also be reversed by this program- ming bit, the FPD and FREF outputs are also interchanged by bit 12 as shown in Table 3. 211 210 29 28 27 26 25 24 23 22 21 20 212 213 1 29 28 27 26 25 24 23 22 21 20 0 ADDRESS PIN 40 BIT 15 PIN 11 BIT 0 NOT USED PHASE DETECTOR STATE CONTROL (SEE TABLE 4) PHASE DETECTOR SENSE CONTROL (SEE TABLE 3) 10-BIT REFERENCE COUNTER Fig. 6a Reference word bit allocation ADDRESS PHASE DETECTOR GAIN CONTROL (SEE TABLE 2) M COUNTER 3-BIT A COUNTER Fig. 6b RF division ratio bit allocation PIN 40 BIT 15 PIN 11 BIT 0 Fig. 6 Programming data format Bit 15 0 0 1 1 Bit 14 0 1 0 1 Current multiplication factor 1·0 1·5 2·5 4·0 Table 2 Table 4 The FPD and FREF signals to the phase detector are available on pins 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. These outputs may be programmed by bits 10 and 11 of word 0 according to Table 4. State 3, where the outputs are disabled by the lock detect circuit, is useful where the user wishes to use an external phase detector. The internal phase/frequency detector may be used to pull the loop into lock and an automatic switch-over to the external phase detector made. When the FPD and FREF outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 Ω may be connected to ground to reduce the fall time of the output pulse. |
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