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SP8852DIGHCAR Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc |
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SP8852DIGHCAR Datasheet(HTML) 7 Page - Zarlink Semiconductor Inc |
7 / 14 page SP8852D 7 Bit 15 Bit 14 Current Multiplication Factor 0 0 1.0 0 1 1.5 1 0 2.5 1 1 4.0 Table 1 Pin 19 current ] Vcc * 1.6V R set I pin 19(mA) multiplication factor 2 p mA radian Phase detector gain + To allow for control direction changes introduced by the design of the PLL, bit 12 on the input bus address 0 can be programmed to reverse the sense of the phase detector by transposing the Fpd and Fref connections. In order that any external phase detector will also be reversed by this programming bit, the Fpd/Fref outputs are also interchanged by bit 12 as shown in Table 2. Output for RF Phase Lag Sense Bit (Bit 12) Pin 20 1 Current Source 0 Current Sink Table 2 The Fpd and Fref signals to the phase detector are available on pin 24 and 25 and may be used to monitor the frequency input to the phase detector or used in conjunction with an external phase detector. These outputs may be programmed by bits 10 and 11 of word 0 according to table 3. State 3 where the outputs are disabled by the lock detect circuit is useful where the user wishes to use an external phase detector. The internal phase/frequency detector may be used to pull the loop into lock and an automatic switch over to the external phase detector made. When the Fpd/Fref outputs are to be used at high frequencies, an external pull down resistor of minimum value 330 W may be connected to ground to reduce the fall time of the output pulse. Bit 11 Bit 10 Phase Detector State 0 0 Phase detector enable Fpd/Fref outputs off 0 1 Phase detector enable Fpd/Fref outputs on 1 0 Phase detector disable by lock detect Fpd/Fref outputs on 1 1 Phase detector disabled Fpd/Fref outputs on Table 3 The charge pump connections to the loop amplifier consist of the charge pump output and the charge pump reference. The matching of the charge pump up and down currents will only be maintained if the charge pump output is held at a voltage equal to the charge pump reference using an operational amplifier to produce a virtual earth condition at pin 20. The lock detect circuit can drive an LED to give visual indication of phase lock or provide an indication to the control system if a pull up resistor is used in place of the LED. A small capacitor connected from the C–lock detector pin to ground may be used to delay lock detect indication and remove glitches produced by momentary phase coincidence during lock up. REFERENCE WORD BIT ALLOCATION 0 ADDRESS BIT 15 NOT USED PHASE DETECTOR SENSE CONTROL PHASE DETECTOR STATE CONTROL see Table 3 TEN BIT REFERENCE COUNTER 29 28 27 26 25 24 23 22 21 20 1 ADDRESS 29 28 27 26 25 24 23 22 21 20 PHASE DETECTOR GAIN CONTROL see Table 1 M COUNTER 3 BIT A COUNTER 213 210 211 212 RF DIVISION RATIO BIT ALLOCATION Fig. 6 Programming data format see Table 2 PIN 40 BIT 0 PIN 11 BIT 0 PIN 11 BIT 15 PIN 40 |
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