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SP8855E Datasheet(PDF) 11 Page - Zarlink Semiconductor Inc

Part # SP8855E
Description  2.8GHz Parallel Load Professional Synthesiser
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

SP8855E Datasheet(HTML) 11 Page - Zarlink Semiconductor Inc

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11
SP8855E
Advance Information
A minimum value for the pull down resistor is 330 Ohms. When
the F
pd
and
F
ref
outputs are disabled the output level will be at
the logic low level of about 3.5V so that the additional supply
current due to the load resistors will be present even when the
outputs are disabled.
Reference input
The reference input circuit functions as an input amplifier or
crystal oscillator. When an external reference signal is used
this is simply AC coupled to pin 28, the base of the input
emitter follower. When a low phase noise synthesiser is
required the reference signal is critical since any noise present
here will be multiplied by the loop. To obtain the lowest
possible phase noise from the SP8855E it is best to use the
highest possible reference input frequency and to divide this
down internally to obtain the required frequency at the phase
detector. The
amplitude of the reference input is also
important, and a level close to the maximum will give the
lowest noise. When the use of a low reference input frequency
say 4-10MHz is essential some advantage may be gained by
using a limiting amplifier such as a CMOS gate to square up
the reference input.
In cases where a suitable reference signal is not available,
it may be more convenient to use the input buffer as a crystal
oscillator in this case the emitter follower input transistor is
connected as a Colpitts oscillator with the crystal connected
from the base to ground and with the feedback necessary for
oscillation provided by a capacitor tap at the emitter. The
arrangement
is
shown
inset
in
Fig.
5.
FROM
CHARGE
PUMP
OUTPUT
C 1
C 2
R 2
TO
VCO
-
+
FROM
CHARGE
PUMP
REFERENCE
Figure 8 - third order loop filter circuit diagram
Loop Filter Design
Generally the third order filter configuration shown in Fig.8
gives better results than the more commonly used second
order because the reference sidebands are reduced. Three
equations are required to determine values for the three
constants where;
τ
1 = C1
τ
2 =
R
2 (C1 + C2)
τ
3
= C
2 R2
The equations are
2
τ
2 =
1
ω
n
2
τ
3
3
τ
3 =
- tan
φ
ο +
1
cos
ω
n
Where;
K
φ
is the phase detector gain factor in mA/radian
K
0
is theVCO gain factor in radian/second/Volt
N
is the total division ratio from VCO to reference
frequency
ω
n
is the natural loop bandwidth
φ
ο
is the phase margin normally set to 45
°
Since the phase detector is linear over a range of 2
π radian,
K
φ can be calculated from
K
φ = Phase comparator current setting/2π mA/radian
These values can now be substituted in equation 1 to obtain
a value for C
1 and equation 2 and 3 used to determine values
for C
2 and R2
EXAMPLE
Calculate values for a loop with the following parameters
Frequency to be synthesised:
1000MHz
Reference frequency
10MHz
Division ratio
1000MHz/10MHz = 100
ω
n natural loop frequency
100KHz
K
0 VCO gain factor
2
π x 10MHz/Volt
φ
0 phase margin
45
°
Phase comparator current
6.3mA
The phase detector gain factor K
φ
= 6.3mA /2
π = 1mA/radian
1
τ
1
=
K
φ K0
N
ω
n
2
1 +
ω
n
2
τ
2
2
1 +
ω
n
2
τ
3
2
1/2
φ
ο


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