CAT9555

7

Doc. No. 8551, Rev. E

© 2007 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

A0, A1, A2: Device Address Inputs

These inputs are used for extended addressing capabil-

addressed on a single bus system. The levels on these

inputs are compared with corresponding bits, A2, A1,

A0, from the slave address byte.

I/O 0.0 to I/O 0.7, I/O 1.0 to I/O 1.7: Input / Output Ports

Any of these pins may be configured as input or output.

The simplified schematic of I/Os is shown in Figure 4.

When an I/O is configured as an input, the Q1 and Q2

output transistors are off creating a high impedance

input with a weak pull-up resistor (typical 100 kohm). If

the I/O pin is configured as an output, the push-pull

output stage is enabled. Care should be taken if an

external voltage is applied to an I/O pin configured as an

output due to the low impedance paths that exist be-

PIN DESCRIPTION

SCL: Serial Clock

The serial clock input clocks all data transferred into or

out of the device. The SCL line requires a pull-up resistor

if it is driven by an open drain output.

SDA: Serial Data/Address

The bidirectional serial data/address pin is used to

transfer all data into and out of the device. The SDA pin

is an open drain output and can be wire-ORed with other

open drain or open collector outputs. A pull-up resistor

the pull-up resistor, Rp, can be calculated based on

minimum and maximum values from Figure 2 and Figure

3 (see Note).

Figure 2. Minimum Rp as a Function of Supply

Figure 3. Maximum Rp Value versus Bus

can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source

(Imax = 3mA) or a switched resistor circuit.

2.5

2

1.5

1

0.5

0

2

2.4

2.8

3.2

3.6

4

4.4

4.8

5.2

5.6

VCC (V)

8.00

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.00

50

100

150

200

250

300

350

400

CBUS (pF)