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ZL50074GAC Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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ZL50074GAC Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
1 / 61 page 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. Features • 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at 65.536 Mbps, 32.768 Mbps or 16.384 Mbps • 16,384 channel x 16,384 channel non-blocking digital TDM switch at 8.192 Mbps • Up to 128 serial TDM input streams, divided into 32 groups with 4 input streams per group • Up to 128 serial TDM output streams, divided into 32 groups with 4 output streams per group • Per-group input bit delay for flexible sampling point selection • Per-group output fractional bit advancement • Four sets of output timing signals for interfacing additional devices • Per-channel constant or variable throughput delay for frame integrity and low latency applications • Per-channel high impedance output control • Per-channel force-high output control • Per-channel message mode • Control interface compatible with Intel and Motorola Selectable 32 bit and 16 bit non- multiplexed buses • Connection Memory block programming • Supports ST-BUS and GCI-Bus standards for input and output timing • IEEE 1149.1 (JTAG) test port • 3.3 V I/O with 5 V tolerant inputs; 1.8 V core Applications • Large Switching Platforms • Central Office Switches • Wireless Base Stations and Controllers • Multi-service Access Platforms January 2006 Ordering Information ZL50074GAC 484 Ball LBGA Trays ZL50074GAG2 484 Ball PBGA** Trays **Pb Free Tin/Silver/Copper -40 °C to +85°C ZL50074 32 K x 32 K Channel TDM Switch with 128 Input and 128 Output Streams Data Sheet Figure 1 - ZL50074 Functional Block Diagram Test Access VSS VDD_IO SToA0 PWR Connection Memory STiA0 ODE Data Memory S/P Microprocessor Interface SToB0 STiB0 VDD_CORE Converter Timing P/S Converter FPi2-0 CKi2-0 CK_SEL1-0 FPo3-0 CKo3-0 Port STiC0 STiD0 SToC0 SToD0 and Control Registers Output Input Timing Timing STiA31 STiB31 STiC31 STiD31 : : SToA31 SToB31 SToC31 SToD31 : : |
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