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ZL50115GAG Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
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ZL50115GAG Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
3 / 95 page ZL50115/16/17/18/19/20 Data Sheet 3 Zarlink Semiconductor Inc. 1.0 Changes Summary The following table captures the changes from the July 2005 issue. The following table captures the changes from the April 2005 issue. The following table captures the changes from the January 2005 issue. The following table captures the changes from the November 2004 issue. Page Item Change 38, 39 Section 4.5 and Section 4.6.2 Added external pull-up/pull-down resistor recommendations for SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK. Page Item Change 49 Section 6.3 Added Section 6.3 SYSTEM_CLK Considerations. Page Item Change Clarified data sheet to indicate ZL5011x supports clock recovery in both synchronous and asynchronous modes of operation. 84 Figure 42 Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. 84 Figure 43 Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform with default MPC8260. Polarity of CPU_DREQ and CPU_SDACK remains programmable through API. Page Item Change 38 Section 4.6.1 Added 5 kohm pulldown recommendation to GPIO signals. |
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