Fully Integrated, Hall Effect-Based Linear Current Sensor with

2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor

ACS712

10

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Chopper Stabilization is an innovative circuit technique that is

used to minimize the offset voltage of a Hall element and an asso-

ciated on-chip amplifier. Allegro patented a Chopper Stabiliza-

tion technique that nearly eliminates Hall IC output drift induced

by temperature or package stress effects. This offset reduction

technique is based on a signal modulation-demodulation process.

Modulation is used to separate the undesired dc offset signal from

the magnetically induced signal in the frequency domain. Then,

using a low-pass filter, the modulated dc offset is suppressed

while the magnetically induced signal passes through the filter.

As a result of this chopper stabilization approach, the output

voltage from the Hall IC is desensitized to the effects of tempera-

ture and mechanical stress. This technique produces devices that

have an extremely stable Electrical Offset Voltage, are immune to

thermal stress, and have precise recoverability after temperature

cycling.

This technique is made possible through the use of a BiCMOS

process that allows the use of low-offset and low-noise amplifiers

in combination with high-density logic integration and sample

and hold circuits.

Chopper Stabilization Technique

Amp

Regulator

Clock/Logic

Hall Element

Low-Pass

Filter

Concept of Chopper Stabilization Technique

+

–

IP+

IP+

IP–

IP–

7

5

5

8

+5 V

U1

LMV7235

VIOUT

GND

6

2

4

4

1

1

2

3

3

FILTER

VCC

ACS712

D1

1N914

R2

100 kΩ

R1

33 kΩ

100 kΩ

Fault

0.1 μF

1 nF

IP+

IP+

IP–

IP–

7

5

8

+5 V

U1

LT1178

Q1

2N7002

VIOUT

GND

6

2

4

1

3

D1

1N914

VCC

ACS712

R4

10 kΩ

R1

1 MΩ

R2

33 kΩ

10 kΩ

R3

330 kΩ

0.1 μF

C1

0.1 μF

0.1 μF

1 nF

C2

0.1 μF

FILTER

IP+

IP+

IP–

IP–

7

5

8

+5 V

D1

1N4448W

VIOUT

GND

6

2

4

1

3

FILTER

VCC

ACS712

R1

10 kΩ

0.1 μF

2 kΩ

1 nF

C1

A-to-D

Converter

Typical Applications

Application 5. 10 A Overcurrent Fault Latch. Fault threshold set by R1 and

R2. This circuit latches an overcurrent fault and holds it until the 5 V rail is

powered down.

Application 2. Peak Detecting Circuit

Application 4. Rectified Output. 3.3 V scaling and rectification application

for A-to-D converters. Replaces current transformer solutions with simpler

ACS circuit. C1 is a function of the load resistance and filtering desired.

R1 can be omitted if the full range is desired.

IP+

IP+

IP–

IP–

7

5

5

8

+5 V

LM321

VIOUT

GND

6

2

4

1

1

4

2

3

3

FILTER

VCC

ACS712

R2

100 kΩ

R1

100 kΩ

R3

3.3 kΩ

0.1 μF

0.01 μF

C1

1000 pF

1 kΩ

Application 3. This configuration increases gain to 610 mV/A

(tested using the ACS712ELC-05A).