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TMDS341APFCR Datasheet(PDF) 7 Page - Texas Instruments |
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TMDS341APFCR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 27 page www.ti.com ABSOLUTE MAXIMUM RATINGS DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS TMDS341A SLLS702B – MAY 2006 – REVISED MARCH 2007 over operating free-air temperature range (unless otherwise noted)(1) UNIT Supply voltage range, VCC(2) –0.5 V to 4 V Anm(3), Bnm 2.5 V to 4 V Voltage range Ym, Zm, VSADJ, PRE, Sn, OE, HPDn –0.5V to 4 V SCLn, SCL_SINK, SDAn, SDA_SINK, HPD_SINK –0.5 V to 6 V Anm, Bnm 5 kV Human body model(4) All pins 4 kV Electrostatic discharge Charged-device model(5) (all pins) 1000 V Machine model (6) (all pins) 250 V See Dissipation Rating Continuous power dissipation Table (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) n = 1, 2, 3; m = 1, 2, 3, 4 (4) Tested in accordance with JEDEC Standard 22, Test Method A114-B (5) Tested in accordance with JEDEC Standard 22, Test Method C101-A (6) Tested in accordance with JEDEC Standard 22, Test Method A115-A DERATING FACTOR (1) TA = 70°C PACKAGE TA ≤ 25°C ABOVE TA = 25°C POWER RATING 80-TQFP 1342 mW 13.42 mW/ °C 738 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. MIN NOM MAX UNIT VCC Supply voltage 3 3.3 3.6 V TA Operating free-air temperature 0 70 °C TMDS DIFFERENTIAL PINS (A/B) VID Receiver peak-to-peak differential input voltage 150 1560 mVp-p VIC Input common mode voltage VCC–0.4 VCC+0.01 V RVSADJ Resistor for TMDS compliant voltage swing range 4.6 4.64 4.68 k Ω AVCC TMDS output termination voltage, see Figure 1 3 3.3 3.6 V RT Termination resistance, see Figure 1 45 50 55 Ω Signaling rate 0 2.25 Gbps CONTROL PINS (PRE; S, OE) VIH LVTTL High-level input voltage 2 VCC V VIL LVTTL Low-level input voltage GND 0.8 V DDC I/O PINS (SCL, SCL_SINK, SDA, SDA_SINK) VI(DDC) Input voltage GND 5.5 V STATUS PINS (HPD_SINK) VIH LVTTL High-level input voltage 2 5.3 V VIL LVTTL Low-level input voltage GND 0.8 V 7 Submit Documentation Feedback |
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