MC33171, MC33172, MC33174, NCV33172

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APPLICATIONS INFORMATION − CIRCUIT DESCRIPTION/PERFORMANCE FEATURES

Although the bandwidth, slew rate, and settling time of the

MC33171/72/74 amplifier family is similar to low power op

amp products utilizing JFET input devices, these amplifiers

offer additional advantages as a result of the PNP transistor

differential inputs and an all NPN transistor output stage.

Because the input common mode voltage range of this

operation is feasible to as low as 3.0 V with the common

mode input voltage at ground potential.

The input stage also allows differential input voltages up

to ±44 V, provided the maximum input voltage range is not

exceeded. Specifically, the input voltages must range

maximum rating table. In practice, although not

voltage by 0.3 V without causing product damage, although

output phase reversal may occur. It is also possible to source

clamping diode without damage or latching, but phase

reversal may again occur. If at least one input is within the

common mode input voltage range and the other input is

within the maximum input voltage range, no phase reversal

will occur. If both inputs exceed the upper common mode

input voltage limit, the output will be forced to its lowest

voltage state.

Since the input capacitance associated with the small

geometry input device is substantially lower (0.8 pF) than

that of a typical JFET (3.0 pF), the frequency response for

a given input source resistance is greatly enhanced. This

becomes evident in D−to−A current to voltage conversion

applications where the feedback resistance can form a pole

with the input capacitance of the op amp. This input pole

creates a 2nd Order system with the single pole op amp and

is therefore detrimental to its settling time. In this context,

lower input capacitance is desirable especially for higher

values of feedback resistances (lower current DACs). This

input pole can be compensated for by creating a feedback

zero with a capacitance across the feedback resistance, if

necessary, to reduce overshoot. For 10 k

W of feedback

resistance, the MC33171/72/74 family can typically settle to

within 1/2 LSB of 8 bits in 4.2

ms, and within 1/2 LSB of 12

bits in 4.8

ms for a 10 V step. In a standard inverting unity

gain fast settling configuration, the symmetrical slew rate is

typically ±2.1 V/

ms. In the classic noninverting unity gain

configuration the typical output positive slew rate is also

2.1 V/

ms, and the corresponding negative slew rate will

usually exceed the positive slew rate as a function of the fall

time of the input waveform.

The all NPN output stage, shown in its basic form on the

equivalent circuit schematic, offers unique advantages over

the more conventional NPN/PNP transistor Class AB output

stage. A 10 k

W load resistance can typically swing within

providing a 28.4 Vpp swing from ±15 V supplies. This large

output swing becomes most noticeable at lower supply

voltages.

The positive swing is limited by the saturation voltage of

transistor Q17, and the voltage drop associated with the

short circuit resistance, R5. For sink currents less than

0.4 mA, the negative swing is limited by the saturation

voltage of the pull−down transistor Q15, and the voltage

drop across R4 and R5. For small valued sink currents, the

above voltage drops are negligible, allowing the negative

currents (> 0.4 mA), diode D3 clamps the voltage across R4.

Thus the negative swing is limited by the saturation voltage

Therefore an unprecedented peak−to−peak output voltage

swing is possible for a given supply voltage as indicated by

the output swing specifications.

ground for single supply applications, the maximum

possible output swing can be achieved for a given supply

voltage. For light load currents, the load resistance will pull

will pull the load resistance near ground during the negative

swing. The load resistance value should be much less than

that of the feedback resistance to maximize pull−up

capability.

Because the PNP output emitter−follower transistor has

been eliminated, the MC33171/72/74 family offers a 15 mA

minimum current sink capability, typically to an output

output can directly source or sink base current from a

common emitter NPN transistor for current switching

applications.

In addition, the all NPN transistor output stage is

inherently faster than PNP types, contributing to the bipolar

amplifier’s improved gain bandwidth product. The

associated high frequency low output impedance (200

W typ

@ 1.0 MHz) allows capacitive drive capability from 0 pF to

400 pF without oscillation in the noninverting unity gain

configuration. The 60° phase margin and 15 dB gain margin,

as well as the general gain and phase characteristics, are

virtually independent of the source/sink output swing

conditions. This allows easier system phase compensation,

since output swing will not be a phase consideration. The AC

characteristics of the MC33171/72/74 family also allow

excellent active filter capability, especially for low voltage

single supply applications.

Although the single supply specification is defined at

5.0 V, these amplifiers are functional to at least 3.0 V @

25°C. However slight changes in parametrics such as

bandwidth, slew rate, and DC gain may occur.