NB4L339_07 datasheet(3/12 Pages) ONSEMI

Part #	NB4L339

Description	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan?뭀ut Buffer

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NB4L339

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Table 4. Pin Description

Name

I/O

Description

1, 8, EP

VEE

−

Negative Supply Voltage

2

CLKA

LVPECL, CML,

LVDS Input

Non−inverted differential input (A). (Note 1)

3

VTA

−

Internal 100−W center−tapped termination pin for CLKA and CLKA (Note 1).

4

CLKA

LVPECL, CML,

LVDS Input

Inverted differential input (A). (Note 1)

5

CLKB

LVPECL, CML,

LVDS Input

Non−inverted differential input (B). (Note 1)

6

VTB

−

Internal 100−W center−tapped termination pin for CLKB and CLKB. (Note 1)

7

CLKB

LVPECL, CML,

LVDS Input

Inverted differential input (B). (Note 1)

9, 16,

25, 32

VCC

−

Positive Supply Voltage

10

CLKSEL

LVCMOS/LVTTL

Asynchronous Clock input select pin. This pin defaults LOW when left open with 80 kW

resistor to VEE.

11

QD1

LVPECL Output

Inverted differential (D1) output. Typically terminated with 50 W resistor to VCC – 2 V

12

QD1

LVPECL Output

Non−inverted Differential (D1) Output. Typically terminated with 50 W resistor to VCC – 2 V.

13

QD0

LVPECL Output

Inverted differential (D0) output. Typically terminated with 50 W resistor to VCC – 2 V.

14

QD0

LVPECL Output

Non−inverted Differential (D0) Output. Typically terminated with 50 W resistor to VCC – 2 V.

15

EN

LVCMOS/LVTTL

Synchronous Output Enable/Disable pin. This pin defaults LOW when left open with 80 kW

resistor to VEE.

17

QC1

LVPECL Output

Inverted differential (C1) output. Typically terminated with 50 W resistor to VCC – 2 V.

18

QC1

LVPECL Output

Non−inverted Differential (C1) Output. Typically terminated with 50 W resistor to VCC – 2 V.

19

QC0

LVPECL Output

Inverted differential (C0) output. Typically terminated with 50 W resistor to VCC – 2 V.

20

QC0

LVPECL Output

Non−inverted Differential (C0) Output. Typically terminated with 50 W resistor to VCC – 2 V.

21

QB1

LVPECL Output

Inverted differential (B1) output. Typically terminated with 50 W resistor to VCC – 2 V.

22

QB1

LVPECL Output

Non−inverted Differential (B1) Output. Typically terminated with 50 W resistor to VCC – 2 V.

23

QB0

LVPECL Output

Inverted differential (B0) output. Typically terminated with 50 W resistor to VCC – 2 V.

24

QB0

LVPECL Output

Non−inverted Differential (B0) Output. Typically terminated with 50 W resistor to VCC – 2 V.

26

MR

LVCMOS/LVTTL

Master Reset Asynchronous. This pin defaults HIGH when left open with 80 kW resistor to

VCC.

27

QA1

LVPECL Output

Inverted differential (A1) output. Typically terminated with 50 W resistor to VCC – 2 V.

28

QA1

LVPECL Output

Non−inverted Differential (A1) Output. Typically terminated with 50 W resistor to VCC – 2 V.

29

QA0

LVPECL Output

Inverted differential (A0) output. Typically terminated with 50 W resistor to VCC – 2 V.

30

QA0

LVPECL Output

Non−inverted Differential (A0) Output. Typically terminated with 50 W resistor to VCC – 2 V.

31

DIVSEL

LVCMOS/LVTTL

Asynchronous Divide Select Pin selects A divide block outputs to divide by 1 or divide by 2.

Defaults LOW when left open, divide−by−1, with 80 kW resistor to VEE.

−

EP

−

Exposed Pad. The exposed pad (EP) on package bottom (see case drawing) is thermally

connected to the die for improved heat transfer out of package and must be attached to a

heat−sinking conduit. The pad is electrically connected to VEE and must be connected to

VEE on the PC board.

1. In the differential configuration when the input termination pin (VTx / VTx) are connected to a common termination voltage or left open, and

if no signal is applied on CLKx / CLKx input then the device will be susceptible to self−oscillation.

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