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NB4L52 Datasheet(PDF) 1 Page - ON Semiconductor

Part # NB4L52
Description  2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB4L52 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 2
1
Publication Order Number:
NB4L52/D
NB4L52
2.5 V/3.3 V/5.0 V Differential
Data/Clock D Flip−Flop
with Reset
Multi−Level Inputs to LVPECL Translator
w/ Internal Termination
The NB4L52 is a differential Data and Clock D flip−flop with a
differential asynchronous Reset. The differential inputs incorporate
internal 50
W termination resistors and will accept PECL, LVPECL,
LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock
transitions from Low to High, Data will be transferred to the
differential LVPECL outputs. The differential Clock inputs allow the
NB4L52 to also be used as a negative edge triggered device. The
device is housed in a small 3x3 mm 16 pin QFN package.
Features
Maximum Input Clock Frequency > 4 GHz Typical
330 ps Typical Propagation Delay
145 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical
Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V
Internal Input Termination Resistors, 50 W
Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,
LVEP, EP, and SG Devices
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
16
NB4L
52
ALYWG
G
1
Data
Clock
Reset
VTD
VTCLK
D
CLK
VTR R
R
D
CLK
Q
Hx
x
L
LL
Z
L
LH
Z
H
Z = LOW to HIGH Transition
x = Don’t Care
Table 1. TRUTH TABLE
Figure 1. Logic Diagram
D
VTD
CLK
VTCLK
VTR
R
Q
Q
(Note: Microdot may be in either location)
1


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