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NB6L16 Datasheet(PDF) 1 Page - ON Semiconductor

Part # NB6L16
Description  2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB6L16 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 6
1
Publication Order Number:
NB6L16/D
NB6L16
2.5V / 3.3V Multilevel Input to
Differential LVPECL/LVNECL
Clock or Data Receiver/
Driver/Translator Buffer
The NB6L16 is a high precision, low power ECL differential clock
or data receiver/driver/translator buffer. The device is functionally
equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With
output transition times of 70 ps, it is ideally suited for high frequency,
low power systems. The device is targeted for Backplane buffering,
GbE clock/data distribution, Fibre Channel distribution and SONET
clock/data distribution applications.
Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV
ECL signals.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
Maximum Input Clock Frequency w 6 GHz Typical
Maximum Input Data Rate Frequency w 6 Gb/s Typical
Low 12 mA Typical Power Supply Current
70 ps Typical Rise/Fall Times
130 ps Input Propagation Delay
On−Chip Reference for ECL Single−Ended Input − VBB Output
PECL Mode Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −2.375 V to −3.465 V
Open Input Default State
LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input
Compatible
Pb−Free Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
MARKING
DIAGRAMS*
6L16
ALYW
G
G
SOIC−8
D SUFFIX
CASE 751
1
8
TSSOP−8
DT SUFFIX
CASE 948R
1
8
1
8
*For additional marking information, refer to
Application Note AND8002/D.
1
8
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
http://onsemi.com
6L16
ALYW
G
(Note: Microdot may be in either location)


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