NB7L11M

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2

Q0

CLK

CLK

56

7

8

16

15

14

13

12

11

10

9

1

2

3

4

NB7L11M

Exposed Pad (EP)

Figure 2. QFN−16 Pinout (Top View)

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Description

1

−

Internal 50 W Termination Pin for CLK

2

CLK

LVPECL, CML,

LVCMOS, LVTTL,

LVDS

Inverted Differential Clock/Data Input. (Note 1)

3

CLK

LVPECL, CML,

LVCMOS, LVTTL,

LVDS

Noninverted Differential Clock/Data Input. (Note 1)

4

−

Internal 50 W Termination Pin for CLK

5,8,13,16

−

to guarantee proper operation.

6

Q1

CML Output

Inverted CLK output 1 with internal 50 W source termination resistor. (Note 2)

7

Q1

CML Output

Noninverted CLK output 1 with internal 50 W source termination resistor. (Note 2)

9,10,11,12

−

to guarantee proper operation.

14

Q0

CML Output

Inverted CLK output 0 with internal 50 W source termination resistor. (Note 2)

15

Q0

CML Output

Noninverted CLK output 0 with internal 50 W source termination resistor. (Note 2)

−

EP

−

Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must

be attached to a heatsinking conduit. It is recommended to connect the EP to the lower

and if no signal is applied on CLK and CLK then the device will be susceptible to self−oscillation.