NB7L86MMN datasheet(8/12 Pages) ONSEMI

Part #	NB7L86MMN

Description	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

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NB7L86M

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Figure 14. AC Reference Measurement

D

Q

tPHL

tPLH

VINPP = VIH(D) − VIL(D)

VOUTPP = VOH(Q) − VOL(Q)

Driver

Device

Receiver

Device

QD

Figure 15. Typical Termination for Output Driver and Device Evaluation

(Refer to Application Note AND8020 − Termination of ECL Logic Devices)

Q

D

VCC

50 W

Z = 50 W

Figure 16. Differential Input Driven

Single−Ended

Figure 17. Differential Inputs Driven

Differentially

Figure 18. Vth Diagram

Figure 19. VCMR Diagram

D

VCC

GND

VIH

VIHmin

VIHmax

Vthmax

Vth

Vthmin

VCMmax

D

VCMR

VCC

GND

D

Vth

D

VILmax

VIL

VILmin

D

VILDmax

VIHDmax

VID = VIHD − VILD

VILDtyp

VIHDtyp

VILDmin

VIHDmin

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