NB7L111MMN datasheet(6/13 Pages) ONSEMI

Part #	NB7L111MMN

Description	2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output

Download	13 Pages

Scroll/Zoom	100%

Manufacturer	ONSEMI [ON Semiconductor]

Direct Link	http://www.onsemi.com

Logo

6 / 13 page

NB7L111M

http://onsemi.com

6

Table 6. AC CHARACTERISTICS VCC = 2.375 V to 2.625 V and 3.135 V to 3.465 V, VEE = 0 V; (Note 10)

Symbol

Characteristic

−40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

VOUTPP Output Voltage Amplitude (@ Vinppmin)

(See Figures 3, 4, 5, and 6)

VCC = 2.375 V to 2.625 V

fin ≤ 3 GHz

fin ≤ 5.5 GHz

VCC = 3.135 V to 3.465 V

fin ≤ 3 GHz

fin ≤ 5.5 GHz

240

115

250

130

330

220

350

250

240

115

250

130

330

220

350

250

240

115

250

130

330

220

350

250

mV

fDATA

Maximum Operating Data Rate

5

6

5

6

5

6

Gb/s

tPLH,

tPHL

Differential Input−to−Output Propagation Delay

@ 1 GHz (See Figures 7 and 11)

CLK−Q

SEL−Q

200

290

240

340

280

390

200

290

240

340

280

390

200

290

240

340

280

390

ps

tSKEW

Duty Cycle Skew (Note 11)

Within Device Skew

Device−to−Device Skew (Note 15)

2

10

15

20

80

2

10

15

20

80

2

10

15

20

80

ps

tJITTER

RMS Random Clock Jitter (Note 13)

fin = 3 GHz

fin = 5.5 GHz

Peak−to−Peak Data Dependent Jitter

(Note 14)

fDATA = 3.125 Gb/s

fDATA = 5 Gb/s

fDATA = 6.125 Gb/s

0.2

6

15

0.5

15

25

0.2

6

15

0.5

15

25

0.2

6

15

0.5

15

25

ps

VINPP

Input Voltage Swing/Sensitivity

(Differential Configuration)

(Note 12 and Figures 3, 4, 5, and 6)

75

400

2500

75

400

2500

75

400

2500

mV

tr

tf

Output Rise/Fall Times @ 1 GHz

(20% − 80%)

50

75

50

75

50

75

ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

10.Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps

(20% − 80%).

11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.

12.VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.

13.Additive RMS jitter with 50% duty cycle clock signal.

14.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS 223−1.

15.Device−to−device skew is measured between outputs under identical transition and conditions @ 1 GHz.

Similar Part No. - NB7L111MMN

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	NB7L11M	202Kb / 11P	2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination January, 2006 ??Rev. 1
	NB7L11M	229Kb / 11P	CML Outputs and Internal Termination August, 2016 ??Rev. 4
	NB7L11MMN	202Kb / 11P	2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination January, 2006 ??Rev. 1
	NB7L11MMNG	202Kb / 11P	2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination January, 2006 ??Rev. 1
	NB7L11MMNG	229Kb / 11P	CML Outputs and Internal Termination August, 2016 ??Rev. 4

More results

Similar Description - NB7L111MMN

Manufacturer	Part #	Datasheet	Description
ON Semiconductor	NBSG111	174Kb / 11P	2.5V/3.3V SiGe Differential 1:10 Clock/Data Driver with RSECL Outputs January, 2007 ??Rev. 8
	NB7L86M	1Mb / 12P	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination January, 2006 ??Rev. 3
	NB7L86M	1Mb / 12P	2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination March, 2012 ??Rev. 7
	NB7VQ58M	1Mb / 9P	1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator with CML Outputs August, 2009 ??Rev. 0
	NB6L295M	194Kb / 13P	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs January, 2010 ??Rev. 4
	NB6L572M	161Kb / 9P	2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator November, 2009 ??Rev. 1
	NB6L295M	199Kb / 13P	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs March, 2012 ??Rev. 5
	NB6L295MMNGEVB	199Kb / 13P	2.5V / 3.3V Dual Channel Programmable Clock/Data Delay with Differential CML Outputs March, 2012 ??Rev. 5
	NBSG14	354Kb / 12P	2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL Outputs August, 2003 ??Rev. 7
Micrel Semiconductor	SY100EP111U	104Kb / 9P	2.5V/3.3V 1:10 DIFFERENTIAL LVPECL/LVECL/HSTL CLOCK DRIVER

More results

NB7L111MMN Datasheet(PDF) 6 Page - ON Semiconductor

NB7L111MMN Datasheet(HTML) 6 Page - ON Semiconductor

Similar Part No. - NB7L111MMN

Similar Description - NB7L111MMN

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet Download

Link URL