NB7N017M

http://onsemi.com

4

Table 2. CE Truth Table

CE

Clock Status

LOW

HIGH

Clock Disabled

Clock Enabled

Table 3. SEL Truth Table

SEL

Active Register

LOW

HIGH

REGa

REGb

Table 4. Register Programming Values for Various Divide Ratios

Pa7/Pb7

Pa6/Pb6

Pa5/Pb5

Pa4/Pb4

Pa3/Pb3

Pa2/Pb2

Pa1/Pb1

Pa0/Pb0

Divide By

0

0

0

0

0

0

0

0

undefined

0

000

000

1

2

0

000

001

0

3

0

000

001

1

4

−

−−−

−−−

−

−

−

−−−

−−−

−

−

1

111

110

1

254

1

111

111

0

255

1

1

1

1

1

1

1

1

256

Table 5. Function Table

MR

Pla

PLb

SEL

CE

CLK

Function

H

X

X

X

X

X

Master Reset (Counter programmed to 0000 0000, REGa and REGb programmed to 1111 1111 and

TC to 1)

L

H

L

X

X

X

REGa is transparent to Pa[0:7]

L

L

H

X

X

X

REGb is transparent Pb[0:7]

L

L

L

L

H

Z

Count; At TC pulse, load counter from REGa

L

L

L

H

H

Z

Count; At TC pulse, load counter from REGb

L

X

X

X

L

X

Hold

X − Don’t Care

H − HIGH

L − LOW

Z − Rising Edge