NB7L216MNG datasheet(9/12 Pages) ONSEMI

Part #	NB7L216MNG

Description	2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination

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NB7L216

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APPLICATION INFORMATION

All NB7L216 inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential

input signal (LVDS, PECL, or CML) are minimum input swing of 75 mV and the maximum input swing of 2500 mV. Within

these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W

environment (Z = 50

W). For output termination and interface, refer to application note AND8020/D.

Table 7. INTERFACING OPTIONS

Interfacing Options

Connections

CML

Connect VTD and VTD to VCC (See Figure 18)

LVDS

Connect VTD and VTD Together (See Figure 20)

AC−COUPLED

Bias VTD and VTD Inputs within Common Mode Range (VCMR) (See Figure 19)

RSECL, PECL, NECL

Standard ECL Termination Techniques (See Figure 13)

LVTTL, LVCMOS

An External Voltage (VTHR) should be Applied to the Unused Complementary Differential Input. Nominal

VTHR is 1.5 V for LVTTL and VCC / 2 for LVCMOS Inputs. This Voltage must be within the

VTHR Specification. (See Figure 21)

50

W

VCC

D

50

W

NB7L216

VCC

VTD

VEE

VCC

Q

50

W 50 W

CML

Driver

VEE

Figure 18. CML to NB7L216 Interface

Q

Z = 50

W

Figure 19. PECL to NB7L216 Interface

50

W

VCC

PECL

Driver

D

50

W

NB7L216

VEE

VBias*

VTD

VEE

RT

VEE

VCC

RT

5.0 V 290

W

3.3 V 150

W

2.5 V

80

W

Recommended RT Values

VTD

VCC

VTD

VBias*

Z = 50

W

Z = 50

W

Z = 50

W

C

*VBias must be within common mode range limits (VCMR)

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