NB100LVEP224FARG datasheet(2/10 Pages) ONSEMI

Part #	NB100LVEP224FARG

Description	2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable

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Manufacturer	ONSEMI [ON Semiconductor]

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NB100LVEP224

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12345678

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All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally

conductive exposed pad on package bottom (see package case drawing) must be attached to a heat−sinking conduit, capable of transfer-

ring 1.2 Watts. This exposed pad is electrically connected to VEE internally.

OE (1)

L

H

Table 1. PIN DESCRIPTION

FUNCTION

ECL Differential Input Clock

ECL Input CLK Select

ECL Output Enable

ECL Differential Outputs

Positive Supply

Negative Supply

CLK0*, CLK0**

CLK1*, CLK1**

CLK_SEL*

OE*

Q0−Q23, Q0−Q23

VCC, VCCO

VEE***

Figure 1. 64−Lead LQFP Pinout (Top View)

Q7

VCCO

Q7

Q6

Q5

Q1

VCCO

Q15

Q16

Q17

VCCO

CLK_SEL

L

H

L

H

Q0−Q23

CLK0

CLK1

L

CLK0

CLK1

H

1. The OE (Output Enable) signal is synchronized with the

falling edge of the LVPECL_CLK signal.

NB100LVEP224

* Pins will default LOW when left open.

** Pins will default HIGH when left open.

***The thermally conductive exposed pad on the bottom of the

package is electrically connected to VEE internally.

9

10

11

1213141516

Q18

Q19

Q20

Q21

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24

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64

Q5

Q4

Q3

Q2

Q1

Table 2. FUNCTION TABLE

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