NBC12439FN datasheet(9/20 Pages) ONSEMI

Part #	NBC12439FN

Description	3.3V/5V Programmable PLL Synthesized Clock Generator

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Manufacturer	ONSEMI [ON Semiconductor]

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NBC12439, NBC12439A

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9

PROGRAMMING INTERFACE

Programming the NBC12439 and NBC12439A is

accomplished by properly configuring the internal dividers

to produce the desired frequency at the outputs. The output

frequency can by represented by this formula:

FOUT = (FXTAL or FREF_EXT ÷ 2) × 2M ÷ N (eq. 1)

This can be simplified to:

FOUT = (FXTAL or FREF_EXT) × M ÷ N

(eq. 2)

where FXTAL is the crystal frequency, M is the loop divider

modulus, and N is the output divider modulus. Note that it

is possible to select values of M such that the PLL is unable

to achieve loop lock. To avoid this, always make sure that M

is selected to be 25 ≤ M ≤ 50 for a 16 MHz input reference.

See Table 11.

Assuming that a 16 MHz reference frequency is used the

above equation reduces to:

FOUT = 16M ÷ N

(eq. 3)

Substituting the four values for N (1, 2, 4, 8) yields:

Table 10. Programmable Output Divider Function

Table

N1

N0

N Divider

FOUT

Output Fre-

quency

Range (MHz)*

FOUT

Step

1

÷1

M × 16

400--800

16 MHz

0

÷2

M × 8

200--400

8MHz

0

1

÷4

M × 4

100--200

4MHz

1

0

÷8

M × 2

50--100

2MHz

*For crystal frequency of 16 MHz.

The user can identify the proper M and N values for the

desired frequency from the above equations. The four output

frequency ranges established by N are 400--800 MHz,

200 -- 400 MHz,

100 -- 200 MHz and

50 -- 100 MHz,

respectively. From these ranges, the user will establish the

value of N required. The value of M can then be calculated

based on Equation 1. For example, if an output frequency of

384 MHz was desired, the following steps would be taken to

identify the appropriate M and N values. 384 MHz falls

within the frequency range set by an N value of 2; thus, N

[1:0]

=

00.

ForN=2, FOUT = 8Mand M= FOUT ÷ 8. Therefore,

M = 384 ÷ 8= 48,so M[6:0]= 0110000.Following thissame

procedure, a user can generate a selected frequency. The size

of the programmable frequency steps of FOUT will be equal

to FXTAL ÷ N.

For input reference frequencies other than 16 MHz, see

Table 11, which shows the usable VCO frequency and M

divider range.

The input frequency and the selection of the feedback

divider M is limited by the VCO frequency range and

fXTAL. M must be configured to match the VCO frequency

range of 400 to 800 MHz in order to achieve stable PLL

operation.

M min = fVCOmin ÷ FXTAL and

(eq. 4)

M max = fVCOmax ÷ FXTAL

(eq. 5)

The value for M falls within the constraints set for PLL

stability. If the value for M fell outside of the valid range, a

different N value would be selected to move M in the

appropriate direction.

The M and N counters can be loaded either through a

parallel or serial interface. The parallel interface is

controlled via the P_LOAD signal such that a LOW to HIGH

transition will latch the information present on the M[6:0]

and N[1:0] inputs into the M and N counters. When the

P_LOAD signal is LOW, the input latches will be

transparent and any changes on the M[6:0] and N[1:0] inputs

will affect the FOUT output pair. To use the serial port, the

S_CLOCK signal samples the information on the S_DATA

line and loads it into a 12 bit shift register. Note that the

P_LOAD signal must be HIGH for the serial load operation

to function. The Test register is loaded with the first three

bits, the N register with the next two, and the M register with

the final nine bits of the data stream on the S_DATA input.

For each register, the most significant bit is loaded first (T2,

N1, and M6). The HIGH to LOW transition on the S_LOAD

input will latch the new divide values into the counters. A

pulse on the S_LOAD pin after the shift register is fully

loaded will transfer the divide values into the counters.

Figures 5 and 6 illustrate the timing diagram for both a

parallel and a serial load of the device synthesizer.

M[6:0] and N[1:0] are normally specified after power--up

through the parallel interface, and then possibly, fine tuned

again through the serial interface. This approach allows the

application to ramp up at one frequency and then change or

fine--tune the clock as the ability to control the serial

interface becomes available.

The TEST output provides visibility for one of the several

internal nodes as determined by the T[2:0] bits in the serial

configuration stream. It is not configurable through the

parallel interface. The T2, T1, and T0 control bits are preset

to ‘000’ when P_LOAD is LOW so that the PECL FOUT

outputs are as jitter--free as possible. Any active signal on the

TEST output pin will have detrimental affects on the jitter

of the PECL output pair. In normal operations, jitter

specifications are only guaranteed if the TEST output is

static. The serial configuration port can be used to select one

of the alternate functions for this pin.

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