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WM8706 Datasheet(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8706 Datasheet(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 26 page  WM8706 Production Data w PD Rev 4.1 July 2005 8 MASTER CLOCK TIMING XTI t XTIL t XTIH t XTIY Figure 1 Master Clock Timing Requirements Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Master Clock Timing Information XTI Master clock pulse width high tXTIH 13 ns XTI Master clock pulse width low tXTIL 13 ns XTI Master clock cycle time tXTIY 26 ns XTI Duty cycle 40:60 60:40 DIGITAL AUDIO INTERFACE BCKIN LRCIN t BCH t BCL t BCY DIN t LRSU t DS t LRH t DH Figure 2 Digital Audio Data Timing Test Conditions AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, XTI = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCKIN cycle time tBCY 40 ns BCKIN pulse width high tBCH 16 ns BCKIN pulse width low tBCL 16 ns LRCIN set-up time to BCKIN rising edge tLRSU 8 ns LRCIN hold time from BCKIN rising edge tLRH 8 ns DIN set-up time to BCKIN rising edge tDS 8 ns DIN hold time from BCKIN rising edge tDH 8 ns |
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