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DIGITAL I/O Min Typ Max Unit Input Voltage HI (VIH) 2.4 V Input Voltage LO (VIL) 0.8 V Input Leakage (IIH @ VIH = 5 V) 10 µA Input Leakage (IIL @ VIL = 0 V) 10 µA Output Voltage HI (VOH @ IOH = –2 mA) 2.4 V Output Voltage LO (VOL @ IOL = 2 mA) 0.4 V Input Capacitance 15 pF DIGITAL TIMING (Guaranteed over –40 °C to +85°C, DV DD = AVDD = 5 V ± 5%. Refer to Figures 17–19.) Min Typ Max Unit tCLKIN CLKIN Period 48 81 780 ns fCLKIN CLKIN Frequency (1/tCLKIN) 1.28 12.288 20.48 MHz tCPWL CLKIN LO Pulsewidth 15 ns tCPWH CLKIN HI Pulsewidth 15 ns tRPWL RESET LO Pulsewidth 50 ns tBPWL BCLK LO Pulsewidth 15 ns tBPWH BCLK HI Pulsewidth 15 ns tDLYCKB CLKIN Rise to BCLK Xmit (Master Mode) 15 ns tDLYBLR BCLK Xmit to L RCK Transition (Master Mode) 15 ns tDLYBWR BCLK Xmit to WCLK Rise 10 ns tDLYBWF BCLK Xmit to WCLK Fall 10 ns tDLYDT BCLK Xmit to DATA/TAG Valid (Master Mode) 10 ns tSETLRBS L RCK Setup to BCLK Sample (Slave Mode) 10 ns tDLYLRDT L RCK Transition to DATA/TAG Valid (Slave Mode) No MSB Delay Mode (for MSB Only) 40 ns tSETWBS WCLK Setup to BCLK Sample (Slave Mode) Data Position Controlled by WCLK Input Mode 10 ns tDLYBDT BCLK Xmit to DATA/TAG Valid (Slave Mode) All Bits Except MSB in No MSB Delay Mode All Bits in MSB Delay Mode 40 ns POWER Min Typ Max Unit Supplies Voltage, Analog and Digital 4.75 5 5.25 V Analog Current 43 52 mA Analog Current–Power-Down (CLKIN Running) 25 µA Digital Current 9.3 12 mA Digital Current–Power-Down (CLKIN Running) 50 µA Dissipation Operation–Both Supplies 263 315 mW Operation–Analog Supply 216 260 mW Operation–Digital Supply 47 55 mW Power-Down–Both Supplies (CLKIN Running) 375 µW Power-Down–Both Supplies (CLKIN Not Running) 375 µW Power Supply Rejection (See TPC 5) 1 kHz 300 mV p-p Signal at Analog Supply Pins 90 dB 20 kHz 300 mV p-p Signal at Analog Supply Pins 68 dB Stop Band (>0.55 × fS)—any 300 mV p-p Signal 110 dB AD1870 REV. A –3– |
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