10

AT89S8252

0401G–MICRO–3/06

Data Memory –

EEPROM and RAM

The AT89S8252 implements 2K bytes of on-chip EEPROM for data storage and 256

bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special

Function Registers. That means the upper 128 bytes have the same addresses as the

SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address

mode used in the instruction specifies whether the CPU accesses the upper 128 bytes

of RAM or the SFR space. Instructions that use direct addressing access SFR space.

For example, the following direct addressing instruction accesses the SFR at location

0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For exam-

ple, the following indirect addressing instruction, where R0 contains 0A0H, accesses the

data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes

of data RAM are available as stack space.

The on-chip EEPROM data memory is selected by setting the EEMEN bit in the

WMCON register at SFR address location 96H. The EEPROM address range is from

000H to 7FFH. The MOVX instructions are used to access the EEPROM. To access off-

chip data memory with the MOVX instructions, the EEMEN bit needs to be set to “0”.

The EEMWE bit in the WMCON register needs to be set to “1” before any byte location

in the EEPROM can be written. User software should reset EEMWE bit to “0” if no fur-

ther EEPROM write is required. EEPROM write cycles in the serial programming mode

are self-timed and typically take 2.5 ms. The progress of EEPROM write can be moni-

tored by reading the RDY/BSY bit (read-only) in SFR WMCON. RDY/BSY = 0 means

Table 5. SPSR – SPI Status Register

SPSR Address = AAH

Reset Value = 00XX XXXXB

SPIF

WCOL

–––

–––

Bit

7

6

543

210

Symbol

Function

SPIF

SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and ES

= 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then reading/writing the

SPI data register.

WCOL

Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, the

result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF bit) are

cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register.

Table 6. SPDR – SPI Data Register

SPDR Address = 86H

Reset Value = unchanged

SPD7

SPD6

SPD5

SPD4

SPD3

SPD2

SPD1

SPD0

Bit

76543210