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AT90S8515 Datasheet(PDF) 25 Page - ATMEL Corporation |
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AT90S8515 Datasheet(HTML) 25 Page - ATMEL Corporation |
25 / 112 page 25 AT90S8515 0841G–09/01 External Reset An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (V RST) on its positive edge, the delay timer starts the MCU after the Time-out period t TOUT has expired. Figure 26. External Reset during Operation Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 42 for details on operation of the Watchdog. Figure 27. Watchdog Reset during Operation Interrupt Handling The AT90S8515 has two 8-bit interrupt mask control registers; GIMSK (General Inter- rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed. For interrupts triggered by events that can remain static (e.g., the Output Compare Register1 matching the value of Timer/Counter1), the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs the next time. When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the |
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