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AT90S8515 Datasheet(PDF) 26 Page - ATMEL Corporation |
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AT90S8515 Datasheet(HTML) 26 Page - ATMEL Corporation |
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26 / 112 page  26 AT90S8515 0841G–09/01 interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software. If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one) and will be executed by order of priority. Note that external level interrupt does not have a flag and will only be remembered for as long as the interrupt condition is active. General Interrupt Mask Register – GIMSK • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge of the INT1 pin or is level-sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program mem- ory address $002. See also “External Interrupts”. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge of the INT0 pin or is level-sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program mem- ory address $001. See also “External Interrupts”. • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and always read as zero. General Interrupt Flag Register – GIFR • Bit 7 – INTF1: External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1 in GIMSK is set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured as level interrupt. Bit 7 6 5 4 3 2 1 0 $3B ($5B) INT1 INT0 – – – – – – GIMSK Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $3A ($5A) INTF1 INTF0 – – – – – – GIFR Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 |
Similar Part No. - AT90S8515_01 |
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Similar Description - AT90S8515_01 |
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