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AT90S2313-4SC Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT90S2313-4SC Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 92 page 7 AT90S2313 0839I–AVR–06/02 General Purpose Register File Figure 6 shows the structure of the 32 general purpose registers in the CPU. Figure 6. AVR CPU General Purpose Working Registers All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the Register File (R16..R31). The general SBC, SUB, CP, AND, OR, and all other operations between two registers or on a single register apply to the entire Register File. As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although the Register File is not physically implemented as SRAM locations, this memory organization pro- vides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. X-register, Y-register, and Z- register The registers R26..R31 have some added functions to their general purpose usage. These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined in Figure 7. Figure 7. X-, Y-, and Z-Registers 70 Addr. R0 $00 R1 $01 R2 $02 … R13 $0D General R14 $0E Purpose R15 $0F Working R16 $10 Registers R17 $11 … R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte 15 0 X-register 7 0 7 0 R27 ($1B) R26 ($1A) 15 0 Y-register 7 0 7 0 R29 ($1D) R28 ($1C) 15 0 Z-register 7 0 7 0 R31 ($1F) R30 ($1E) |
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