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NCP3521 Datasheet(PDF) 7 Page - ON Semiconductor |
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NCP3521 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 10 page NCP3520/NCP3521 http://onsemi.com 7 DETAILED OPERATING DESCRIPTION General The NCP3520/NCP3521 are LDO Regulator Controllers. An external NFET device sets the current capability allowing for designer selection. Features include an undervoltage lockout for both the integrated circuit supply Pin VCC, and the supply pin for the external FET connection to the drain of the FET. The NRCS (Non Rush Current on Startup) feature prevents high currents through the external FET (drain−source). The external capacitor setting component used in NRCS is also used for short circuit protection (SCP). The device also has an enable feature allowing it to go into a low supply current sleep mode demanded by most modern day feature rich systems when not in use. Thermal shutdown functionality protects the IC from damage caused from excessively high temperatures appearing on the IC. Output Driver Output current drive capability is determined by the designer’s choice of external MOSFET (NFET). Power dissipated in the driver can be controlled by the voltage applied to VD. VD should be kept low to minimize power dissipation and high enough to support regulated operation at the desired output current. It should also be noted the output capacitor (VO to GND) value supports regulation during high speed transient events until the system loop can respond to any voltage dips to drive the external FET. High Speed Control Unlike most linear regulators whose reaction to overvoltage events is to turn off the upper driver and let the external load and resistor feedback network quench the incident, the NCP3520/21 include a 1.2 mA pulldown through the VS Pin. This keeps overshoot to a minimum during powerup. During turn−off and thermal overload, the pulldown current is increased from 1.2 mA to 220 mA to provide an even faster turn−off time. Power On Reset A 50 ms power on reset circuit is built into the IC acting as a digital filter and performing housekeeping activity during a short circuit event. The timer effects three areas of operation. 1. EN turn on delay. Upon detection of an EN high, there is a 50 ms delay to when the internal circuitry turns on and the gate pin (G) goes high. A low on EN resets the timer. 2. VCC startup delay. If VCC drops out below the undervoltage lockout voltage and restored above its hysteresis value, a 50 ms time is also observed from reinitiation of VCC and G going high. This is recognized to be different from the EN turn on delay by the active circuitry of the voltage reference, NRCS circuitry, and VS high current pulldown. 3. Device startup into a short circuit. Further details are available on this subject under the heading “Starting Up Into A Short Circuit”. Normal Powerup/Down The NRCS (Non Rush Current on Startup) timer controls the output driver during powerup. The output driver voltage (VG) is controlled during powerup. The voltage on NRCS is mimicked to provide a duplicate voltage on VFB. When 1.2 V is reached normal operation of the error amplifier and feedback network take over. Regulation is maintained in the loop around 1.2 V. The NRCS pin rises up to 1 V. At 1 V, the NRCS capacitor is discharged fully at a 300 mA (min) rate. The IC enters a standby mode capable of short circuit detection. A 20 mA pullup current source is used to charge the external NRCS capacitor linearly and maintain a predictable powerup. A recommended 0.01 mF will provide a 325 ms powerup time. Alternative times can be programmed with this equation: T + C(NRCS) * VFB INRCS (eq. 1) Rush current during startup can be calculated by I = COUT * VO / T. The NRCS circuit is not active during powerdown. Normal circuit operation will be maintained unless VCC_UVLO or VD_UVLO cause the gate drive output to turn off. NRCS 1.0 V VS / VFB 1.2 V EN 3 V 0.65 V Figure 13. Powerup (NCP3520 (1.2 V) Version Shown) A standby mode for short circuit is entered here. Error amplifier takes control here. 50 ms |
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Similar Description - NCP3521 |
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