7

1001E–MICRO–6/05

AT89C4051

9.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The

mode is invoked by software. The content of the on-chip RAM and all the special functions regis-

ters remain unchanged during this mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset.

P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external

pullups are used.

It should be noted that when idle is terminated by a hardware reset, the device normally

resumes program execution, from where it left off, up to two machine cycles before the internal

reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but

access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a

port pin when Idle is terminated by reset, the instruction following the one that invokes Idle

should not be one that writes to a port pin or to external memory.

10. Power-down Mode

In the power-down mode the oscillator is stopped and the instruction that invokes power-down is

the last instruction executed. The on-chip RAM and Special Function Registers retain their val-

ues until the power-down mode is terminated. The only exit from power-down is a hardware

reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be

activated before V

enough to allow the oscillator to restart and stabilize.

P1.0 and P1.1 should be set to “0” if no external pullups are used, or set to “1” if external

pullups are used.

11. Brown-out Detection

pulled high. When V

delay of typically 15 msec. The nominal brown-out detection threshold is 2.1V ± 10%.

2.1V

2.1V

PORT PIN

INTERNAL RESET

15 msec.