NCP5201

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6

DETAILED OPERATION DESCRIPTIONS

General

The NCP5201 Dual DDR Power Controller combines

the efficiency of a PWM controller for the VDDQ supply

with the simplicity of a linear regulator for the VTT

memory

termination voltage. VTT is designed to

automatically track at half VDDQ.

The inclusion of an internal PWM switching FET for

VDDQ standby operation, both VDDQ and VTT power

good voltage monitors, soft−start, undervoltage detection,

and thermal shutdown, make this device a total power

solution for high current DDR memory systems. The IC is

packaged in 5

× 6 QFN−18.

IC Control States

The state decode logic and internal control functions are

powered by 5.0 V VSTBY. An internal voltage reference

and bias current block is enabled when VSTBY exceeds

3.8 V. Once VREF reaches its regulation voltage, internal

signal _VREFGD will be asserted HIGH. This transition

wakes up the voltage monitor block, which in turn detects

whether the VSTBY and VCC voltages are within certain

preset regulation levels. If they are, the voltage monitor

generates an internal HIGH VSTGD and 12 VGD

respectively.

There is an internal detection for 100% duty cycle of

TGDDQ switching, if it occurs, an internal signal

MAXDTY is asserted HIGH.

The logic control block accepts an external signal at the

S3_EN pin and internal voltage monitor signals MXDTY,

12 VGD and VSTGD to decode the operating states in

accordance with Table 1. PWRGD is an open−drain logic

output that signifies VDDQ and VTT are both in regulation

in the S0 mode.

Table 1. Control Logic State Truth Table

Input Conditions

Operation Mode

VSTGD

S3_EN

12 VGD

MAXDTY

Prev.

Next

Low

X

X

X

X

S5

High

Low

Low

X

X

S5

High

Low

High

X

X

S0

High

High

High

Low

S0

S0

High

High

X

High

S0

S3

High

High

Low

X

S0

S3

High

High

X

X

S3

S3

VDDQ Regulator in Normal (SO) mode

The VDDQ regulator in S0 mode is a switching

synchronous rectification buck controller directly driving

two external N−Channel power FETs. An external resistor

divider sets the nominal output voltage. The control

architecture is voltage mode fixed frequency PWM with

external compensation, and with switching frequency

fixed at 250 kHz

±10%. As can be observed from Figure 1,

the VDDQ output voltage is divided down and fed back to

pin FBDDQ. This voltage connects to the inverting input

of the internal error amplifier while the amplifier’s

noninverting input is connected to an internal voltage

reference, VREF (= 1.3 V). The amplifier compares the

feedback voltage to VREF and outputs an error signal to the

PWM comparator. This error signal is compared with a

fixed frequency RAMP waveform derived from the

internal oscillator to generate a pulse−width−modulated

signal. This PWM signal drives the external N−Channel

Power FETs via the TGDDQ and BGDDQ pins. External

inductor L and COUT1 filter the output waveform, which

is subsequently fed back to FBDDQ via a resistor voltage

divider to close the loop at VDDQ = VFBQ (1 + R2/R1).

An adjustable soft−start is implemented, activated each

time the IC exits state S5. When in normal mode, and

regulation of VDDQ is detected, signal INREGDDQ will

go HIGH to notify the Control Logic block.

Tolerance of VDDQ

The tolerance of VFBQ and the ratio of external resistor

divider R7/R10 both impact the precision of VDDQ. With

the control loop in regulation, VDDQ = (VFBQ)

(1 + R7/R10). With a worst case (for all valid operating

conditions) VFBQ tolerance of

±2%, a worst case range of

±2.5% for VDDQ will be assured if the ratio R7/R10 is

specified as 0.9230

±1%.

Synchronous Rectification

For enhanced efficiency, an active synchronous switch is

used to eliminate the conduction loss contributed by the

forward voltage of a diode or Schottky diode rectifier.

Adaptive nonoverlap timing control of the complementary

gate drive output signals is provided to reduce large

shoot−through currents, which degrade efficiency.