NCP5322A_07 datasheet(8/31 Pages) ONSEMI

Part #	NCP5322A

Description	Two?뭁hase Buck Controller with Integrated Gate Drivers and 5?묪it DAC

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NCP5322A

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8

ELECTRICAL CHARACTERISTICS (continued) (0

°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCCH1 = VCCH2 < 20 V; 4.5 V <

VCCL = VCCL1 = VCCL2 < 14 V; CGATE = 3.3 nF, RR(OSC) = 32.4 kW, CCOMP = 1.0 nF, CREF = 0.1 mF, CSS = 0.1 mF,

DAC Code 10000 (1.45 V), CVCC = 1.0 mF; unless otherwise specified.)

Characteristic

Unit

Max

Typ

Min

Test Conditions

General Electrical Specifications

VCCH1 or VCCH2 Operating Current

VFB = COMP (no switching)

−

3.2

4.5

mA

VCCL Start Threshold

GATEs switching, Soft Start charging

4.05

4.3

4.5

V

VCCL Stop Threshold

GATEs stop switching, Soft Start discharging

3.75

4.1

4.35

V

VCCL Hysteresis

GATEs not switching, Soft Start not charging

100

200

300

mV

VCCH1 Start Threshold

GATEs switching, Soft Start charging

1.8

2.0

2.2

V

VCCH1 Stop Threshold

GATEs stop switching, Soft Start discharging

1.55

1.75

1.90

V

VCCH1 Hysteresis

GATEs not switching, Soft Start not charging

100

200

300

mV

Reference Output

VREF Output Voltage

0 mA < I(VREF) < 1.0 mA

3.2

3.3

3.4

V

Internal Ramp

Ramp Height @ 50% PWM

Duty−Cycle

CS1 = CS2 = CSREF.

−

125

−

mV

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

PIN SYMBOL

FUNCTION

SO−28L

1

COMP

Output of the error amplifier and input for the PWM

comparators.

2

VFB

Voltage Feedback Pin. To use Adaptive Voltage Positioning

(AVP) select an offset voltage at light load and connect a

resistor between VFB and VOUT. The input current of the VFB

pin and the resistor value determine output voltage offset for

zero output current. Short VFB to VOUT for no AVP.

3

VDRP

Current sense output for AVP. The offset of this pin above the

DAC voltage is proportional to the output current. Connect a

resistor from this pin to VFB to set amount AVP or leave this

pin open for no AVP. This pin’s maximum working voltage is

2.3 Vdc.

4−5

CS1−CS2

Current sense inputs. Connect current sense network for the

corresponding phase to each input. The input voltages to

these pins must be kept within 105 mV of CSREF or pulse−

by−pulse current limit will be tripped.

6

CSREF

Reference for Current Sense Amplifiers, input to the Power

Good comparators, and fast feedback connection to the

PWM comparator. To balance input offset voltages between

the inverting and noninverting inputs of the Current Sense

Amplifiers, connect a resistor between CSREF and the output

voltage. The value should be 1/3 of the value of the resistors

connected to the CSx pins. The input voltage to this pin must

not exceed the maximum DAC (VID) setting by more than

100 mV or the internal PWM comparator may saturate.

7

PWRGD

Power Good Output. Open collector output goes low when

CSREF (VOUT) is out of regulation.

8−12

VID4−VID0

Voltage ID DAC inputs. These pins are internally pulled up to

3.3 V if left open.

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