9

AT25P1024

1082I–SEEPR–7/06

READ SEQUENCE (READ):

Reading the AT25P1024 via the SO (Serial Output) pin

requires the following sequence. After the CS line is pulled low to select a device, the

READ op-code is transmitted via the SI line followed by the byte address to be read

(Refer to Table 10). Upon completion, any data on the SI line will be ignored. The data

(D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is

to be read, the CS line should be driven high after the data comes out. The read

sequence can be continued since the byte address is automatically incremented and

data will continue to be shifted out. When the highest address is reached, the address

counter will roll over to the lowest address allowing the entire memory to be read in one

continuous read cycle.

WRITE SEQUENCE (WRITE):

In order to program the AT25P1024, two separate

instructions must be executed. First, the device must be write enabled via the WREN

instruction. Then a Write instruction may be executed. Also, the address of the memory

location(s) to be programmed must be outside the protected address field location

selected by the block write protection level. During an internal write cycle, all commands

will be ignored except the RDSR instruction.

A Write Instruction requires the following sequence. After the CS line is pulled low to

select the device, the Write op-code is transmitted via the SI line followed by the byte

address and the data (D7-D0) to be programmed (Refer to Table 9). Programming will

start after the CS pin is brought high. The low-to-high transition of the CS pin must occur

during the SCK low time immediately after clocking in the D0 (LSB) data bit.

The Ready/Busy status of the device can be determined by initiating a Read Status

Register (RDSR) Instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,

the write cycle has ended. Only the Read Status Register instruction is enabled during

the write programming cycle.

The AT25P1024 is capable of a 128-byte Page Write operation ONLY. Content of the

page in the array will not be guaranteed if less than 128 bytes of data is received (byte

operation is not supported). After each byte of data is received, the seven low order

address bits are internally incremented by one; the high order bits of the address will

remain constant. If more than 128 bytes of data are transmitted, the address counter will

roll over and the previously written data will be overwritten. The AT25P1024 is automat-

ically returned to the write disable state at the completion of a write cycle.

NOTE: If the device is not Write enabled (WREN), the device will ignore the Write

instruction and will return to the standby state, when CS is brought high. A new CS fall-

ing edge is required to re-initiate the serial communication.

1

Low

1

Protected

Writable

Protected

X

High

0

Protected

Protected

Protected

X

High

1

Protected

Writable

Writable

Table 10. Address Key

Address

AT25P1024

A

N

A

Don’t Care Bits

A

Table 9. WPEN Operation (Continued)

WPEN

WP

WEN

Protected

Blocks

Unprotected Blocks

Status Register